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ds07-13743-2e fujitsu semiconductor data sheet copyright?2006-2007 fujitsu limited all rights reserved ?check sheet? is seen at the following support page url : http://www.fujitsu.com/global/services/micr oelectronics/product/micom/support/index.html ?check sheet? lists the minimal require ment items to be checked to prevent problems beforehand in system development. be sure to refer to the ?check sheet? for the latest cautions on development. 16-bit proprietary microcontroller cmos f 2 mc-16lx mb90880 series mb90f882(s)/f883(s)/f883a(s)/f884(s)/f884a(s) mb90882(s)/883(s)/884(s)/v880(a)-101/-102 description the mb90880 series is a general-purpose 16-bit microcon troller, designed by fujitsu, for process control of devices such as consumer appliances, which requi re high-speed real-time processing capabilities. the instruction set of the f 2 mc-16lx cpu core retains the sa me at architecture as the f 2 mc* 1 family, with further refinements including high-level language instructio ns, an expanded addressing mode, enhanced multiplier- divider instructions and bit processing. in addition, a 32-bit accumulator is built in to enable long word processing. as its peripheral resources, the mb90880 series has a 16- bit ppg, multi-function serial interface (software switch over enabled for sio, uart and i 2 c* 2 ) , 10-bit a/d converter, 16-bit i/o timer, 8/16-bit up-down counter, base timer (software switch over enabled for 16-bit relo ad timer, pwc timer, ppg timer and pwm timer) , dtp / external interrupt and chip select pins. *1 : f 2 mc is the abbreviation of fujitsu flexible microcontroller. *2 : purchase of fujitsu i 2 c components conveys a license under the philips i 2 c patent rights to use, these components in an i 2 c system provided that the system conforms to the i 2 c standard specific ation as defined by philips.
mb90880 series 2 features clock minimum instruction execution time : 30. 3 ns / 4.125 mhz source oscillation eight times (in internal operation : 33 mhz/3.3 v 0.3 v) pll clock multiplication system maximum memory space 16 mbytes instruction set optimized for control applications supported data types : bit, byte, word and long word standard addressing modes : 23 types enhanced high-precision calculation realized by 32-bit accumulator signed multiplication/division instructio ns and extended reti instruction functions instruction set supporting high-level langua ge (c language) and multi-task operations introduction of system stack pointer symmetrical instruction set and barrel shift instructions improved execution speed 4-byte queue powerful interrupt functions eight priority levels programmable; external interrupts : 24 data transfer functions ( dmac) up to 16 channels built-in rom flash rom : 256, 384 and 512 kbytes ; mask rom : 256, 384 and 512 kbytes built-in ram flash ram : 16, 24 and 30 kbytes ; mask ram : 16, 24 and 30 kbytes general-purpose ports dual clock product : up to 81 channels; single clock product : up to 83 channels a/d converter rc successive approximation conversion type : 20 channels (resolution : 8 or 10 bits) multi-function serial interface 7 channels (software switchable between for sio, uart and i 2 c) 16-bit ppg 8 channels 8/16-bit up-down counter/timer event input pins : 6 8-bit up-down counters : 2 8-bit reload/compare registers : 2 base timer 4 channels (software switchable between 16-bit rel oad timer, pwc timer, ppg timer, and pwm timer) 16-bit i/o timer input capture 2 channels, output compare 6 channels, free run timer 1 channel built-in dual clock generator low power consumption modes stop mode, sleep mode, cpu intermittent operati on mode, watch timer, time base timer mode package qfp-100/lqfp-100 process cmos technology power supply voltage 3v : single power supply operation
mb90880 series 3 product lineup (continued) item name mb90882 (s) mb90883 (s) mb90884 (s) mb90f882 (s) mb90f883 (s) / mb90f883a (s) mb90f884 (s) / mb90f884a (s) class mask rom product flash memory product rom size 256 kbytes 384 kbytes 512 kb ytes 256 kbytes 384 kbytes 512 kbytes ram size 16 kbytes 24 kbytes 30 kbytes 16 kbytes 24 kbytes 30 kbytes cpu functions number of instructions instruction bit length instruction length data bit length minimum execution time : 351 : 8 bits, 16 bits : 1 to 7 bytes : 1 bit, 8 bits, 16 bits : 30.3 ns (machine clock : 33 mhz) the maximum operating frequency of mb90f 883(s) and mb90f884(s) is 25 mhz. ports general-purpose i/o ports : up to 81 for dual clock model, up to 83 for single clock model general-purpose i/o ports (cmos output) multi-function serial interface 7 channels (software switchable between sio, uart & i 2 c) 16-bit ppg timer 8 channels 8/16-bit up-down counter/timer event input pins : 6, 8- bit up-down counters : 2 8-bit reload/compare registers : 2 16-bit i/o timer 16-bit free run timer number of channels : 1 overflow interrupt output compare (ocu) number of channels : 6 pin input source : match signal of compare register input capture (icu) number of channels : 2 rewriting register by pin input (rising, falling or both edges) dtp/external interrupt circuit external interrupt pins : 24 channels (edge/level support) base timer 4 channels (software switchable between 16-bit reload timer, pwc timer, ppg timer, and pwm timer) in mb90f883(s) and mb90f884(s), p24/ tio0, p25/tio1, p26/tio2, and p27/tio3 cannot be used as input function. time base timer 18-bit counter interrupt interval : 1.0 ms, 4.1 ms, 16.4 ms , 131.1 ms (source oscillation : 4 mhz) a/d converter conversion accuracy : 8 or 10 bits can be switched single conversion mode (selected channel converted only once) scan conversion mode (multiple successive channels converted) successive conversion mode (select ed channel converted repeatedly) stop conversion mode (selected cha nnel converted and stopped repeatedly) watchdog timer reset generation interval : 3.58 ms, 14.33 ms, 57.23ms, 458.75 ms (source oscillation : 4 mhz, minimum value)
mb90880 series 4 (continued) item name mb90882 (s) mb90883 (s) mb90884 (s) mb90f882 (s) mb90f883 (s) / mb90f883a (s) mb90f884 (s) / mb90f884a (s) low power consumption (standby) modes sleep, stop, cpu intermittent operat ion, watch timer, time base timer flash memory ? flash security/ write-protect feature (not available in mb90f883(s), mb90f884(s), mb90f883a(s), and mb90f884a(s)) process cmos technology
mb90880 series 5 pin assignments (top view) (fpt-100p-m06) * : dual clock product is sub clock oscillation pin. 100 99 9 8 97 96 95 94 9 3 92 91 90 8 9 88 8 7 8 6 8 5 8 4 83 8 2 8 1 1 8 0 2 79 3 7 8 4 77 5 76 6 75 7 74 8 7 3 9 72 10 71 11 70 12 69 1 3 6 8 14 67 15 66 16 65 17 64 1 8 6 3 19 62 20 61 21 60 22 59 2 3 5 8 24 57 25 56 26 55 27 54 2 8 5 3 29 52 3 0 51 3 1 3 2 33 3 4 3 5 3 6 3 7 38 3 9 40 41 42 4 3 44 45 46 47 4 8 49 50 qfp-100 p0 3 /ad0 3 /d0 3 /irq 3 p02/ad02/d02/irq2 p01/ad01/d01/irq1 p00/ad00/d00/irq0 p57/clk/ppg7 p56/rdy/ppg6 p55/hak/ppg5 p54/hrq/ppg4 p5 3 /wrh/irq2 3 p52/wrl p51/rd p50/ale pa 3 /(ppg7)/irq22 pa2/(ppg6)/irq21 dv ss dvcc pa1/(ppg5)/irq20 pa0/(ppg4)/irq19 p 8 7/irq1 8 /adtg p 8 6/uck0 p 8 5/uo0 p 8 4/ui0 p 83 /irq17 p 8 2/irq16/uck6 p 8 1/uo6 p 8 0/irq15/ui6 r s t md0 md1 md2 p24/a20/tio0 p25/a21/tio1 p26/a22/tio2 p27/a2 3 /tio 3 p 3 0/a00/zin0/ui1 p 3 1/a01/ain0/uo1 p 3 2/a02/bin0/uck1 p 33 /a0 3 /ui2 p 3 4/a04/uo2 p 3 5/a05/zin1/uck2 p 3 6/a06/ain1/irq 8 p 3 7/a07/bin1/irq9 p40/a0 8 /x0a * p41/a09/x1a * vcc v ss c p42/a10/ui 3 p4 3 /a11/uo 3 p44/a12/uck 3 p45/a1 3 /ui4 p46/a14/uo4 p47/a15/uck4 p90/c s 0/an 8 p91/c s 1/an9 p92/c s 2/an10 p9 3 /c s3 /an11 p94/an12 p95/(ui 3 )/an1 3 p96/(uo 3 )/an14 p2 3 /a19/ppg 3 p22/a1 8 /ppg2 p21/a17/ppg1 p20/a16/ppg0 p17/ad15/d15/in1 p16/ad14/d14/in0 p15/ad1 3 /d1 3 /out5 x0 x1 v ss vcc p14/ad12/d12/out4 p1 3 /ad11/d11/out 3 p12/ad10/d10/out2 p11/ad09/d09/out1 p10/ad0 8 /d0 8 /out0 p07/ad07/d07/irq7 p06/ad06/d06/irq6 p05/ad05/d05/irq5 p04/ad04/d04/irq4 p97/(uck 3 )/an15 avcc avrh p70/an16 av ss p60/an0 p61/an1 p62/an2 p6 3 /an 3 p64/an4 p65/an5 p66/an6 p67/an7 v ss p71/(ui4)/irq10/an17 p72/(uo4)/irq11/an1 8 p7 3 /(uck4)/irq12/an19 p74/irq1 3 /ui5 p75/uo5 p76/irq14/uck5
mb90880 series 6 (top view) (fpt-100p-m20) * : dual clock product is sub clock oscillation pin. 100 99 9 8 97 96 95 94 9 3 92 91 90 8 9 88 8 7 8 6 8 5 8 4 83 8 2 8 1 8 0 79 7 8 77 76 75 74 7 3 72 71 70 69 6 8 67 66 65 64 6 3 62 61 60 59 5 8 57 56 55 54 5 3 52 1 2 3 4 5 6 7 8 9 10 11 12 1 3 14 15 16 17 1 8 19 20 21 22 2 3 24 25 51 26 27 2 8 29 3 0 3 1 3 2 33 3 4 3 5 3 6 3 7 38 3 9 40 41 42 4 3 44 45 46 47 4 8 49 50 lqfp-100 p26/a22/tio2 p27/a2 3 /tio 3 p 3 0/a00/zin0/ui1 p 3 1/a01/ain0/uo1 p 3 2/a02/bin0/uck1 p 33 /a0 3 /ui2 p 3 4/a04/uo2 p 3 5/a05/zin1/uck2 p 3 6/a06/ain1/irq 8 p 3 7/a07/bin1/irq9 p40/a0 8 /x0a * p41/a09/x1a * vcc v ss c p42/a10/ui 3 p4 3 /a11/uo 3 p44/a12/uck 3 p45/a1 3 /ui4 p46/a14/uo4 p47/a15/uck4 p90/c s 0/an 8 p91/c s 1/an9 p92/c s 2/an10 p9 3 /c s3 /an11 p00/ad00/d00/irq0 p57/clk/ppg7 p56/rdy/ppg6 p55/hak/ppg5 p54/hrq/ppg4 p5 3 /wrh/irq2 3 p52/wrl p51/rd p50/ale pa 3 /(ppg7)/irq22 pa2/(ppg6)/irq21 dv ss dvcc pa1/(ppg5)/irq20 pa0/(ppg4)/irq19 p 8 7/irq1 8 /adtg p 8 6/uck0 p 8 5/uo0 p 8 4/ui0 p 83 /irq17 p 8 2/irq16/uck6 p 8 1/uo6 p 8 0/irq15/ui6 r s t md0 p25/a21/tio1 p24/a20/tio0 p2 3 /a19/ppg 3 p22/a1 8 /ppg2 p21/a17/ppg1 p20/a16/ppg0 p17/ad15/d15/in1 p16/ad14/d14/in0 p15/ad1 3 /d1 3 /out5 x0 x1 v ss vcc p14/ad12/d12/out4 p1 3 /ad11/d11/out 3 p12/ad10/d10/out2 p11/ad09/d09/out1 p10/ad0 8 /d0 8 /out0 p07/ad07/d07/irq7 p06/ad06/d06/irq6 p05/ad05/d05/irq5 p04/ad04/d04/irq4 p0 3 /ad0 3 /d0 3 /irq 3 p02/ad02/d02/irq2 p01/ad01/d01/irq1 p94/an12 p95/(ui 3 )/an1 3 p96/(uo 3 )/an14 p97/(uck 3 )/an15 avcc avrh p70/an16 av ss p60/an0 p61/an1 p62/an2 p6 3 /an 3 p64/an4 p65/an5 p66/an6 p67/an7 v ss p71/(ui4)/irq10/an17 p72/(uo4)/irq11/an1 8 p7 3 /(uck4)/irq12/an19 p74/irq1 3 /ui5 p75/uo5 p76/irq14/uck5 md2 md1
mb90880 series 7 pin descriptions (continued) pin no. pin name i/o circuit type* 3 function lqfp * 1 qfp * 2 13 p26 d general-purpose i/o port a22 in multiplex mode, it serves as higher address output pin (a22) when corresponding bit in external address output control register (hacr) is set to "0". in non-multiplex mode, it serves as higher address output pin (a22) when corresponding bit in external address output control register (hacr) is set to "0". tio2 base timer i/o pin (ch.2) 24 p27 d general-purpose i/o port a23 in multiplex mode, it serves as higher address output pin (a23) when corresponding bit in external address output control register (hacr) is set to "0". in non-multiplex mode, it serves as higher address output pin (a23) when corresponding bit in external address output control register (hacr) is set to "0". tio3 base timer i/o pin (ch.3) 35 p30 e general-purpose i/o port a00 serves as an external address pin in non-multiplex mode. zin0 8/16-bit up-down counter/timer input pin (ch.0) ui1 multi-function serial input pin 46 p31 e general-purpose i/o port a01 serves as an external address pin in non-multiplex mode. ain0 8/16-bit up-down counter/timer input pin (ch.0) uo1/ (sda1) multi-function serial output pin 57 p32 e general-purpose i/o port a02 serves as an external address pin in non-multiplex mode. bin0 8/16-bit up-down counter/timer input pin (ch.0) uck1/ (scl1) multi-function serial clock i/o pin 68 p33 e general-purpose i/o port a03 serves as an external address pin in non-multiplex mode. ui2 multi-function serial input pin 79 p34 e general-purpose i/o port a04 serves as an external address pin in non-multiplex mode. uo2/ (sda2) multi-function serial output pin
mb90880 series 8 (continued) pin no. pin name i/o circuit type* 3 function lqfp * 1 qfp * 2 810 p35 e general-purpose i/o port a05 serves as an external address pin in non-multiplex mode. zin1 8/16-bit up-down counter/timer input pin (ch.1) uck2/ (scl2) multi-function serial clock i/o pin 911 p36 d general-purpose i/o port a06 serves as an external address pin in non-multiplex mode. ain1 8/16-bit up-down counter/timer input pin (ch.1) irq8 external interrupt input pin 10 12 p37 d general-purpose i/o port a07 serves as an external address pin in non-multiplex mode. bin1 8/16-bit up-down counter/timer input pin (ch.1) irq9 external interrupt input pin 11 13 p40 a/d general-purpose i/o port a08 serves as an external address pin in non-multiplex mode. x0a 32 khz oscillator connecting pin 12 14 p41 a/d general-purpose i/o port a09 serves as an external address pin in non-multiplex mode. x1a 32 khz oscillator connecting pin 13 15 vcc - power supply pin 14 16 vss - power supply pin (gnd) 15 17 c - regulator stabilization capacity connecting pin 16 18 p42 e general-purpose i/o port a10 serves as an external address pin in non-multiplex mode. ui3 multi-function serial input pin 17 19 p43 e general-purpose i/o port a11 serves as an external address pin in non-multiplex mode. uo3/ (sda3) multi-function serial output pin 18 20 p44 e general-purpose i/o port a12 serves as an external address pin in non-multiplex mode. uck3/ (scl3) multi-function serial clock i/o pin 19 21 p45 e general-purpose i/o port a13 serves as an external address pin in non-multiplex mode. ui4 multi-function serial input pin
mb90880 series 9 (continued) pin no. pin name i/o circuit type* 3 function lqfp * 1 qfp * 2 20 22 p46 e general-purpose i/o port a14 serves as an external address pin in non-multiplex mode. uo4/ (sda4) multi-function serial output pin 21 23 p47 e general-purpose i/o port a15 serves as an external address pin in non-multiplex mode. uck4/ (scl4) multi-function serial clock i/o pin 22 24 p90 h general-purpose i/o port cs0 chip select 0 an8 analog input pin 23 25 p91 h general-purpose i/o port cs1 chip select 1 an9 analog input pin 24 26 p92 h general-purpose i/o port cs2 chip select 2 an10 analog input pin 25 27 p93 h general-purpose i/o port cs3 chip select 3 an11 analog input pin 26 28 p94 h general-purpose i/o port an12 analog input pin 27 29 p95 k general-purpose i/o port an13 analog input pin (ui3) multi-function serial input pin (when set by p9fsr register) 28 30 p96 k general-purpose i/o port an14 analog input pin (uo3)/ (sda3) multi-function serial output pi n (when set by p9fsr register) 29 31 p97 k general-purpose i/o port an15 analog input pin (uck3)/ (scl3) multi-function serial clock i/o pin (when set by p9fsr register) 30 32 avcc - a/d converter power supply pin 31 33 avrh - a/d converter external reference power supply pin 32 34 p70 h general-purpose i/o port an16 analog input pin
mb90880 series 10 (continued) pin no. pin name i/o circuit type* 3 function lqfp * 1 qfp * 2 33 35 avss - a/d converter power supply pin 34 36 p60 h general-purpose i/o port an0 analog input pin 35 37 p61 h general-purpose i/o port an1 analog input pin 36 38 p62 h general-purpose i/o port an2 analog input pin 37 39 p63 h general-purpose i/o port an3 analog input pin 38 40 p64 h general-purpose i/o port an4 analog input pin 39 41 p65 h general-purpose i/o port an5 analog input pin 40 42 p66 h general-purpose i/o port an6 analog input pin 41 43 p67 h general-purpose i/o port an7 analog input pin 42 44 vss - power supply pin (gnd) 43 45 p71 k general-purpose i/o port irq10 external interrupt input pin an17 analog input pin (ui4) multi-function serial input pin (when set by p7fsr register) 44 46 p72 k general-purpose i/o port irq11 external interrupt input pin an18 analog input pin (uo4)/ (sda4) multi-function serial output pi n (when set by p7fsr register) 45 47 p73 k general-purpose i/o port irq12 external interrupt input pin an19 analog input pin (uck4)/ (scl4) multi-function serial clock i/o pin (when set by f7fsr register) 46 48 p74 g general-purpose i/o port irq13 external interrupt input pin ui5 multi-function serial input pin
mb90880 series 11 (continued) pin no. pin name i/o circuit type* 3 function lqfp * 1 qfp * 2 47 49 p75 g general-purpose i/o port uo5/ (sda5) multi-function serial output pin 48 50 p76 g general-purpose i/o port irq14 external interrupt input pin uck5/ (scl5) multi-function serial clock i/o pin 49 51 md2 l operation mode specification input pin 50 52 md1 l operation mode specification input pin 51 53 md0 l operation mode specification input pin 52 54 rst b reset input pin 53 55 p80 g general-purpose i/o port irq15 external interrupt input pin ui6 multi-function serial input pin 54 56 p81 g general-purpose i/o port uo6/ (sda6) multi-function serial output pin 55 57 p82 g general-purpose i/o port irq16 external interrupt input pin uck6/ (scl6) multi-function serial clock i/o pin 56 58 p83 i general-purpose i/o port irq17 external interrupt input pin 57 59 p84 g general-purpose i/o port ui0 multi-function serial input pin 58 60 p85 g general-purpose i/o port uo0/ (sda0) multi-function serial output pin 59 61 p86 g general-purpose i/o port uck0/ (scl0) multi-function serial clock i/o pin 60 62 p87 i general-purpose i/o port irq18 external interrupt input pin adtg external trigger input pin, when a/d converter is used. 61 63 pa0 j general-purpose i/o port irq19 external interrupt input pin (ppg4) ppg timer output pin (when set by pafsr register)
mb90880 series 12 (continued) pin no. pin name i/o circuit type* 3 function lqfp * 1 qfp * 2 62 64 pa1 j general-purpose i/o port irq20 external interrupt input pin (ppg5) ppg timer output pin (when set by pafsr register) 63 65 dvcc - pa port power supply pin 64 66 dvss - pa port power supply pin (gnd) 65 67 pa2 j general-purpose i/o port irq21 external interrupt input pin (ppg6) ppg timer output pin (when set by pafsr register) 66 68 pa3 j general-purpose i/o port irq22 external interrupt input pin (ppg7) ppg timer output pin (when set by pafsr register) 67 69 p50 f general-purpose i/o port ale serves as address latch enable signal (ale) pin in external bus mode. 68 70 p51 f general-purpose i/o port rd serves as read strobe output (rd ) pin in external bus mode. 69 71 p52 f general-purpose i/o port wrl serves as lower data write strobe output (wrl ) pin in external bus mode, and serves as a general-pur pose i/o port when wre bit in epcr register is "0". 70 72 p53 f general-purpose i/o port wrh serves as higher data write strobe output (wrh ) pin in external bus mode with 16-bit bus width, and serves as a general-purpose i/o port when wre bit in epcr register is "0". irq23 external interrupt input pin 71 73 p54 f general-purpose i/o port hrq serves as hold request input (hrq) pin in external bus mode, and serves as a general-purpose i/o port when hde bit in epcr register is "0". ppg4 ppg timer output pin 72 74 p55 f general-purpose i/o port hak serves as hold acknowledge output (hak ) pin in external bus mode, and serves as a general-purpose i/o port when hde bit in epcr register is "0". ppg5 ppg timer output pin
mb90880 series 13 (continued) pin no. pin name i/o circuit type* 3 function lqfp * 1 qfp * 2 73 75 p56 f general-purpose i/o port rdy serves as external ready input (r dy) pin in external bus mode, and serves as a general-purpose i/o por t when rye bit in epcr register is "0". ppg6 ppg timer output pin 74 76 p57 f general-purpose i/o port clk serves as machine cycle clock output (clk) pin in external bus mode, and serves as a general-pur pose i/o port when cke bit in epcr register is "0". ppg7 ppg timer output pin 75 77 p00 c general-purpose i/o port ad00/ d00 in multiplex mode, it serves as lower external address/data bus i/o pin. serves as lower external data bus output pin in non-multiplex mode. irq0 external interrupt input pin 76 78 p01 c general-purpose i/o port ad01/ d01 serves as an external address/lower data bus i/o pin in multiplex mode. serves as a lower external data bus output pin in non-multiplex mode. irq1 external interrupt input pin 77 79 p02 c general-purpose i/o port ad02/ d02 serves as an external address/lower data bus i/o pin in multiplex mode. serves as a lower external data bus output pin in non-multiplex mode. irq2 external interrupt input pin 78 80 p03 c general-purpose i/o port ad03/ d03 serves as an external address/lower data bus i/o pin in multiplex mode. serves as a lower external data bus output pin in non-multiplex mode. irq3 external interrupt input pin 79 81 p04 c general-purpose i/o port ad04/ d04 in multiplex mode, it serves as lower external address/data bus i/o pin. serves as a lower external data bus output pin in non-multiplex mode. irq4 external interrupt input pin
mb90880 series 14 (continued) pin no. pin name i/o circuit type* 3 function lqfp * 1 qfp * 2 80 82 p05 c general-purpose i/o port ad05/ d05 in multiplex mode, it serves as lower external address/data bus i/o pin. serves as a lower external data bus output pin in non-multiplex mode. irq5 external interrupt input pin 81 83 p06 c general-purpose i/o port ad06/ d06 in multiplex mode, it serves as lower external address/data bus i/o pin. serves as a lower external data bus output pin in non-multiplex mode. irq6 external interrupt input pin 82 84 p07 c general-purpose i/o port ad07/ d07 in multiplex mode, it serves as lower external address/data bus i/o pin. serves as a lower external data bus output pin in non-multiplex mode. irq7 external interrupt input pin 83 85 p10 c general-purpose i/o port ad08/ d08 in multiplex mode, it serves as higher external address/data bus i/o pin. in non-multiplex mode, it serves as higher external data output pin. out0 output compare event output pin 84 86 p11 c general-purpose i/o port ad09/ d09 in multiplex mode, it serves as higher external address/data bus i/o pin. in non-multiplex mode, it serves as higher external data output pin. out1 output compare event output pin 85 87 p12 c general-purpose i/o port ad10/ d10 in multiplex mode, it serves as higher external address/data bus i/o pin. in non-multiplex mode, it serves as higher external data output pin. out2 output compare event output pin 86 88 p13 c general-purpose i/o port ad11/ d11 in multiplex mode, it serves as higher external address/data bus i/o pin. in non-multiplex mode, it serves as higher external data output pin. out3 output compare event output pin
mb90880 series 15 (continued) pin no. pin name i/o circuit type* 3 function lqfp * 1 qfp * 2 87 89 p14 c general-purpose i/o port ad12/ d12 in non-multiplex mode, it serves as higher external data output pin. out4 output compare event output pin 88 90 vcc - power supply pin 89 91 vss - power supply pin (gnd) 90 92 x1 a main oscillator connecting pin 91 93 x0 a main oscillator connecting pin 92 94 p15 c general-purpose i/o port ad13/ d13 in multiplex mode, it serves as higher external address/data bus i/o pin. in non-multiplex mode, it serves as higher external data output pin. out5 output compare event output pin 93 95 p16 c general-purpose i/o port ad14/ d14 in multiplex mode, it serves as higher external address/data bus i/o pin. in non-multiplex mode, it serves as higher external data output pin. in0 trigger input pin for input capture ch.0 94 96 p17 c general-purpose i/o port ad15/ d15 in multiplex mode, it serves as higher external address/data bus i/o pin. in non-multiplex mode, it serves as higher external data output pin. in1 trigger input pin for input capture ch.1 95 97 p20 d general-purpose i/o port a16 in multiplex mode, it serves as higher address output pin (a16) when corresponding bit in external address output control register (hacr) is set to "0". in non-multiplex mode, it serves as higher address output pin (a16) when corresponding bit in external address output control register (hacr) is set to "0". ppg0 ppg timer output pin 96 98 p21 d general-purpose i/o port a17 in multiplex mode, it serves as higher address output pin (a17) when corresponding bit in external address output control register (hacr) is set to "0". in non-multiplex mode, it serves as higher address output pin (a17) when corresponding bit in external address output control register (hacr) is set to "0". ppg1 ppg timer output pin
mb90880 series 16 (continued) *1 : lqfp : fpt-100p-m20 *2 : qfp : fpt-100p-m06 *3 : for the i/o circuit type, refer to ? i/o circuit type?. pin no. pin name i/o circuit type* 3 function lqfp * 1 qfp * 2 97 99 p22 d general-purpose i/o port a18 in multiplex mode, it serves as higher address output pin (a18) when corresponding bit in external address output control register (hacr) is set to "0". in non-multiplex mode, it serves as higher address output pin (a18) when corresponding bit in external address output control register (hacr) is set to "0". ppg2 ppg timer output pin 98 100 p23 d general-purpose i/o port a19 in multiplex mode, it serves as higher address output pin (a19) when corresponding bit in external address output control register (hacr) is set to "0". in non-multiplex mode, it serves as higher address output pin (a19) when corresponding bit in external address output control register (hacr) is set to "0". ppg3 ppg timer output pin 99 1 p24 d general-purpose i/o port a20 in multiplex mode, it serves as higher address output pin (a20) when corresponding bit in external address output control register (hacr) is set to "0". in non-multiplex mode, it serves as higher address output pin (a20) when corresponding bit in external address output control register (hacr) is set to "0". tio0 base timer i/o pin (ch.0) 100 2 p25 d general-purpose i/o port a21 in multiplex mode, it serves as higher address output pin (a21) when corresponding bit in external address output control register (hacr) is set to "0". in non-multiplex mode, it serves as higher address output pin (a21) when corresponding bit in external address output control register (hacr) is set to "0". tio1 base timer i/o pin (ch.1)
mb90880 series 17 i/o circuit type (continued) type circuit remarks a oscillation feedback resistance x1, x0 : approx. 1 m ? x1a, x0a : approx. 10 m ? standby control provided b hysteresis input with pull-up resistor c input pull-up resistor control provided cmos level output hysteresis input cmos input (in external bus mode) d cmos level output hysteresis input e cmos level output hysteresis input i 2 c level hysteresis input x1, x1a x0, x0a p-ch n-ch xo u t standby control signal r r hysteresis input p-ch p-ch n-ch r pull-up control signal cmos input hysteresis input standby control for input shutdown p-ch n-ch r hysteresis input standby control for input shutdown p-ch n-ch r hysteresis input i 2 c level hysteresis input standby control for input shutdown
mb90880 series 18 (continued) type circuit remarks f cmos level output hysteresis input cmos input (in external bus mode) g cmos level output (open-drain control provided) 5v tolerant hysteresis input i 2 c level hysteresis input h cmos level output hysteresis input analog input i cmos level output (open-drain control provided) 5v tolerant hysteresis input p-ch n-ch r cmos input hysteresis input standby control for input shutdown p-ch n-ch r open-drain control signal hysteresis input i 2 c level hysteresis input standby control for input shutdown p-ch n-ch r analog input hysteresis input standby control for input shutdown p-ch n-ch r open-drain control signal hysteresis input standby control for input shutdown
mb90880 series 19 (continued) type circuit remarks j cmos/level output (high-current type) hysteresis input k cmos level output hysteresis input analog input i 2 c level hysteresis input l flash memory product cmos level input high-voltage control for flash test provided mask rom product hysteresis input p-ch n-ch r hysteresis input standby control for input shutdown p-ch n-ch r analog input hysteresis input i 2 c level hysteresis input standby control for input shutdown n-ch n-ch n-ch n-ch r control signal mode input diffused resistor flash memory product r hysteresis input mask rom product
mb90880 series 20 handling devices 1. maximum rated voltages for the prevention of latch-up be cautious not to exceed the absolute maximum rating. cmos ics may cause latch-up, when a voltage higher than v cc or lower than v ss is applied to input or output pins other than medium-to-high resistant pins, or w hen a voltage exceeding the rating is applied between vcc and vss pins. if latch-up occurs, the power supply current increases rapidly, sometimes re sulting in thermal breakdown of the device. take the utmost care not to let it occur. likewise, care must be taken not to allow the analog power supply (av cc , avrh) and analog input to exceed the digital power supply (v cc ) when turning on or off any analog system. 2. handling unused pins leaving unused input pins open may caus e a malfunction or latch-up which leads to fatal damage to the device. therefore, they must be pulled up or down through at least 2 k ? resistance. also, any unused i/o pin should be left open in the output state, or set to the input st ate and handled in the same way as an unused input pin. 3. notes on using external clock even when an external clock is being used, oscillation stab ilization wait time is required for a power-on reset or release from sub clock mode or stop mode. note that 25 mhz is the upper limit on the external clock that can be used. the following diagram shows an example of using an external clock. 4. handling power supply pins (v cc /v ss ) when multiple vcc and vss pins supply pins are used, a ll the power supply pins must be connected to external power and ground lines due to the devi ce design, to reduce latch-up and un wanted radiation, prevent abnormal operation of strobe signals caused by the rise in the gr ound level and to conform to the total output current rating. make sure to connect the vcc and vss pins of this devi ce via lowest impedance to po wer lines. it is recommended that a bypass capacitor of around 0.1 f be placed between the vcc and vss pins near the device. 5. crystal oscillator circuit noises around x0/x1 or x0a/x1a pins may cause abnorma l operations. it is strong ly recommended to provide bypass capacitors via shortest distance from x0/x1, x0a/x1a pins, crystal oscillator (or ceramic oscillator) and ground lines and also not to allow the li nes of the oscillation circuit to cross the lines of other circuits. this will ensure stable operations of the prin ted circuit boards. please ask each cr ystal maker to evaluate the oscillational characteristics of the crystal and this device. 6. notes on pll clock mode operation if an oscillator comes off or clock input stops during pll clock mode operation, this microcontroller may continue its operation using a free-running frequency from a self-e xcited oscillation circuit within pll. this is not a guaranteed operation. x0 x1 open
mb90880 series 21 7. power-on and power-off sequence of a/d converter and analog input turn on the a/d converters (av cc , avrh) and analog inputs (an0 to an19) after turning on the digital power supply (v cc ) . during power-off, turn off the digital power supply (v cc ) after turning off the a/d converters and analog inputs (an0 to an19) . in this case, make sure that avrh does not exceed av cc during the power-on/power-off procedure. also make sure that the input voltage does not exceed av cc when a pin which is also used as an analog input is used as an input port. 8. handling power supply pins on a/d converter-mounted models make sure to achieve "av cc = avrh = v cc " and "av ss = v ss " in connecting the circuits, even when not using the a/d converter function. 9. note on power-up to prevent the internal regulator from malfuncti oning, maintain the voltage rise time at 50 s (between 0.2v and 2.7v) or more during power-up. 10. stabilization of power supply even when the v cc power supply voltage is within the specified operating range, it may still cause the device to malfunction, if the power supply changes rapidly. for stabilization reference, it is recommended to control the supply voltage so that v cc ripple variations (p-p values) at commercial frequencies (50/60 hz) fall below 10 % of the standard v cc supply voltage and the coefficient of fluctuat ion does not exceed 0. 1 v/ms at instantaneous power switching. 11. writing to flash memory for serial writing to flash memory, alwa ys make sure that the operating voltage v cc is between 3.13v and 3.6v. for normal writing to flash memory, always make sure that the operating voltage v cc is between 3.0v and 3.6v. 12. p90/cs0 pins p90/cs0 pins output ?l? during writing flas h serial. do not input from external. 13. note of mb90f883 (s) , mb90f884 (s) maximum operating frequency is 25 mhz. the base timer cannot use p24/tio0, p25/tio1 , p26/tio2, and p27/tio3 as input function. mb90f883(s) and mb90f884(s) do not contain the fl ash security feature and write-protect feature.
mb90880 series 22 block diagram ram rom x0, x1, r s t x0a, x1a md0 to md2 ui0 to ui6 uo0 to uo6 uck0 to uck6 avcc avrh av ss adtg an0 to an19 ain0, ain1 bin0, bin1 zin0, zin1 8888888 7 8 p00 to p07 p10 to p17 p20 to p27 p 3 0 to p 3 7 p40 to p47 p50 to p57 p60 to p67 p70 to p76 p 8 0 to p 8 7 8 p90 to p97 4 pa 0 to pa 3 in0, in1 tio0 to tio 3 irq0 to irq2 3 24 ppg0 to ppg7 out0 to out5 clock control circuit multifunction serial sio/uart/i 2 c mode switching enabled 10-bit a/d converter cpu f 2 mc-16lx series core i/o port interrupt controller 16-bit ppg 8/16-bit up-down counter/timer external interrupt i/o timer 16-bit input capture 2 channels 16-bit output compare 6 channels 16-bit free-run timer 16-bit base timer reload timer/pwm/pwc mode switching enabled note : the i/o ports shown in the diagr am above are shared by other built-in function blocks. they cannot be used as i/o ports when used as pins for a built-in module. f 2 m c - 1 6 l x b u s dmac
mb90880 series 23 memory map note : the image of the rom data in the ff band appears at the top of the 00 bank in order to enable efficient use of the c compiler small memory model. the lower 16- bit address for the ff bank will be assigned to the same address, so that tables in rom can be referenc ed without declaring a "far" indication with the pointer. for example, when accessing the address 00c000 h , the actual access is to address ffc000 h in rom. here the ff bank rom area exceeds 32 kbytes, it is not possible to see the entire area in the 00 bank image. therefore, the rom data in ff8000 h to ffffff h can be seen in the 00 b ank image, while the data in ff0000 h to ff7fff h can only be seen in the ff bank. parts no. address #1 address #2 address #3 mb90882 (s) fc0000 h 008000 h , fixed 004100 h mb90f882 (s) fc0000 h 004100 h mb90883 (s) fa0000 h 006100 h mb90f883 (s) / mb90f883a (s) fa0000 h 006100 h mb90884 (s) f80000 h 007900 h mb90f884 (s) / mb90f884a (s) f80000 h 007900 h mb90v880 (s) (f80000 h ) 007900 h ffffff h 010000 h 000100 h 0000f0 h 000000 h ram ram ram 007900 h peripheral area single chip mode rom area rom area image of ff bank register internal rom external bus rom area rom area image of ff bank peripheral area external rom external bus : internal : external : access prohibited register register peripheral area peripheral area peripheral area peripheral area address #1 address #2 address #3
mb90880 series 24 f 2 mc-16l cpu programming model dedicated register general-purpose register processor status ah al dpr pcb dtb usb ssb adb usp ssp ps pc accumulator user stack pointer system stack pointer processor status program counter direct page register program bank register data bank register user stack bank register system stack bank register additional data bank register 8 bits 16 bits 32 bits r1 r0 r 3 r2 r5 r4 r7 r6 rw0 rw1 rw2 rw 3 0001 8 0 h + rp 10 h rw4 rw5 rw6 rw7 rl0 rl1 rl2 rl 3 m s bl s b 16 bits ilm b it 15 b it 1 3 p s rp ccr b it 12 b it 8 b it 7 b it 0
mb90880 series 25 i/o map (continued) address register abbreviation register name r/w resource initial value 000000 h pdr0 port 0 data register r/w port 0 xxxxxxxx b 000001 h pdr1 port 1 data register r/w port 1 xxxxxxxx b 000002 h pdr2 port 2 data register r/w port 2 xxxxxxxx b 000003 h pdr3 port 3 data register r/w port 3 xxxxxxxx b 000004 h pdr4 port 4 data register r/w port 4 xxxxxxxx b 000005 h pdr5 port 5 data register r/w port 5 xxxxxxxx b 000006 h pdr6 port 6 data register r/w port 6 xxxxxxxx b 000007 h pdr7 port 7 data register r/w port 7 xxxxxxxx b 000008 h pdr8 port 8 data register r/w port 8 xxxxxxxx b 000009 h pdr9 port 9 data register r/w port 9 xxxxxxxx b 00000a h pdra port a data register r/w port a xxxxxxxx b 00000b h uder up-down timer input enable register r/w up-down timer input control xx000000 b 00000c h ilsr0 serial input level selection register 0 r/w multi-function serial control 00000000 b 00000d h ilsr1 serial input level selection register 1 r/w 00000000 b 00000e h ilsr2 serial input level selection register 2 r/w ---00000 b 00000f h disabled 000010 h ddr0 port 0 direction register r/w port 0 00000000 b 000011 h ddr1 port 1 direction register r/w port 1 00000000 b 000012 h ddr2 port 2 direction register r/w port 2 00000000 b 000013 h ddr3 port 3 direction register r/w port 3 00000000 b 000014 h ddr4 port 4 direction register r/w port 4 00000000 b 000015 h ddr5 port 5 direction register r/w port 5 00000000 b 000016 h ddr6 port 6 direction register r/w port 6 00000000 b 000017 h ddr7 port 7 direction register r/w port 7 -0000000 b 000018 h ddr8 port 8 direction register r/w port 8 00000000 b 000019 h ddr9 port 9 direction register r/w port 9 00000000 b 00001a h ddra port a direction register r/w port a ----0000 b 00001b h ader0 analog input enable register 0 r/w port 6, a/d 11111111 b 00001c h ader1 analog input enable register 1 r/w port 9, a/d 11111111 b 00001d h ader2 analog input enable register 2 r/w port 7, a/d ----1111 b 00001e h rdr0 port 0 input resistance register r/w port 0 (pull-up resistance control) 00000000 b 00001f h rdr1 port 1 input resistance register r/w port 1 (pull-up resistance control) 00000000 b
mb90880 series 26 (continued) address register abbreviation register name r/w resource initial value 000020 h smr0 serial bus mode register ch.0 r/w multi-function serial ch.0 $$$$$$$$ b 000021 h scr0/ibcr0 scr0/ibcr0 serial bus control register/i 2 c bus control register ch.0 r/w $$$$$$$$ b 000022 h escr0/ ibsr0 extended communication control register/i 2 c bus status register ch.0 r/w $$$$$$$$ b 000023 h ssr0 serial status register ch.0 r/w $$$$$$$$ b 000024 h rdr00/ tdr00 transmission/reception data register 0 ch.0 r,w $$$$$$$$ b 000025 h rdr10/ tdr10 transmission/reception data register 1 ch.0 r,w $$$$$$$$ b 000026 h bgr00 baud rate generator register 0 ch.0 r/w $$$$$$$$ b 000027 h bgr10 baud rate generator register 1 ch.0 r/w $$$$$$$$ b 000028 h isba0 7-bit slave address register ch.0 r/w 00000000 b 000029 h ismk0 7-bit slave address mask register ch.0 r/w 01111111 b 00002a h smr1 serial bus mode register ch.1 r/w multi-function serial ch.1 $$$$$$$$ b 00002b h scr1/ibcr1 serial bus control register / i 2 c bus control register ch.1 r/w $$$$$$$$ b 00002c h escr1/ ibsr1 extended communication control register / i 2 c bus status register ch.1 r/w $$$$$$$$ b 00002d h ssr1 serial status register ch.1 r/w $$$$$$$$ b 00002e h rdr01/ tdr01 transmission/reception data register 0 ch.1 r,w $$$$$$$$ b 00002f h rdr11/ tdr11 transmission/reception data register 1 ch.1 r,w $$$$$$$$ b 000030 h bgr01 baud rate generator register 0 ch.1 r/w $$$$$$$$ b 000031 h bgr11 baud rate generator register 1 ch.1 r/w $$$$$$$$ b 000032 h isba1 7-bit slave address register ch.1 r/w 00000000 b 000033 h ismk1 7-bit slave address mask register ch.1 r/w 01111111 b 000034 h adcsl lower a/d control status register r/w a/d converter 00011110 b 000035 h adcsh higher a/d control status register r/w 00000000 b 000036 h adcrl lower a/d data register r xxxxxxxx b 000037 h adcrh higher a/d data register r 111111xx b 000038 h adsrl lower a/d conversion channel setting register r/w 00000000 b 000039 h adsrh higher a/d conversion channel setting register r/w 00000000 b 00003a h reserved
mb90880 series 27 (continued) address register abbreviation register name r/w resource initial value 00003b h pacsr1 address detection control status register 1 r/w address match detection function 00000000 b 00003c h olsr0 output level selection register 0 r/w port 7 (n-ch open-drain control) -000---- b 00003d h olsr1 output level selection register 1 r/w port 8 (n-ch open-drain control) 00000000 b 00003e h smr2 serial bus mode register ch.2 r/w multi-function serial ch.2 $$$$$$$$ b 00003f h scr2/ibcr2 serial bus control register / i 2 c bus control register ch.2 r/w $$$$$$$$ b 000040 h escr2/ ibsr2 extended communication control register / i 2 c bus status register ch.2 r/w $$$$$$$$ b 000041 h ssr2 serial status register ch.2 r/w $$$$$$$$ b 000042 h rdr02/ tdr02 transmission/reception data register 0 ch.2 r,w $$$$$$$$ b 000043 h rdr12/ tdr12 transmission/reception data register 1 ch.2 r,w $$$$$$$$ b 000044 h bgr02 baud rate generator register 0 ch.2 r/w $$$$$$$$ b 000045 h bgr12 baud rate generator register 1 ch.2 r/w $$$$$$$$ b 000046 h isba2 7-bit slave address register ch.2 r/w 00000000 b 000047 h ismk2 7-bit slave address mask register ch.2 r/w 01111111 b 000048 h smr3 serial bus mode register ch.3 r/w multi-function serial ch.3 $$$$$$$$ b 000049 h scr3/ibcr3 serial bus control register / i 2 c bus control register ch.3 r/w $$$$$$$$ b 00004a h escr3/ ibsr3 extended communication control register / i 2 c bus status register ch.3 r/w $$$$$$$$ b 00004b h ssr3 serial status register ch.3 r/w $$$$$$$$ b 00004c h rdr03/ tdr03 transmission/reception data register 0 ch.3 r,w $$$$$$$$ b 00004d h rdr13/ tdr13 transmission/reception data register 1 ch.3 r,w $$$$$$$$ b 00004e h bgr03 baud rate generator register 0 ch.3 r/w $$$$$$$$ b 00004f h bgr13 baud rate generator register 1 ch.3 r/w $$$$$$$$ b 000050 h isba3 7-bit slave address register ch.3 r/w 00000000 b 000051 h ismk3 7-bit slave address mask register ch.3 r/w 01111111 b 000052 h smr4 serial bus mode register ch.4 r/w multi-function serial ch.4 $$$$$$$$ b 000053 h scr4/ibcr4 serial bus control register / i 2 c bus control register ch.4 r/w $$$$$$$$ b
mb90880 series 28 (continued) address register abbreviation register name r/w resource initial value 000054 h escr4/ ibsr4 extended communication control register / i 2 c bus status register ch.4 r/w multi-function serial ch.4 $$$$$$$$ b 000055 h ssr4 serial status register ch.4 r/w $$$$$$$$ b 000056 h rdr04/ tdr04 transmission/reception data register 0 ch.4 r,w $$$$$$$$ b 000057 h rdr14/ tdr14 transmission/reception data register 1 ch.4 r,w $$$$$$$$ b 000058 h bgr04 baud rate generator r egister 0 ch.4 r/w $$$$$$$$ b 000059 h bgr14 baud rate generator register 1 ch.4 r/w $$$$$$$$ b 00005a h isba4 7-bit slave address register ch.4 r/w 00000000 b 00005b h ismk4 7-bit slave address mask register ch.4 r/w 01111111 b 00005c h smr5 serial bus mode register ch.5 r/w multi-function serial ch.5 $$$$$$$$ b 00005d h scr5/ibcr5 serial bus control register / i 2 c bus control register ch.5 r/w $$$$$$$$ b 00005e h escr5/ ibsr5 extended communication control register / i 2 c bus status register ch.5 r/w $$$$$$$$ b 00005f h ssr5 serial status register ch.5 r/w $$$$$$$$ b 000060 h rdr05/ tdr05 transmission/reception data register 0 ch.5 r,w $$$$$$$$ b 000061 h rdr15/ tdr15 transmission/reception data register 1 ch.5 r,w $$$$$$$$ b 000062 h bgr05 baud rate generator register 0 ch.5 r/w $$$$$$$$ b 000063 h bgr15 baud rate generator register 1 ch.5 r/w $$$$$$$$ b 000064 h isba5 7-bit slave address register ch.5 r/w 00000000 b 000065 h ismk5 7-bit slave address mask register ch.5 r/w 01111111 b 000066 h occp0 lower output compare register (ch.0) r/w 16-bit i/o timer output compare (ch.0 to ch.5) 00000000 b 000067 h higher output compare register (ch.0) 00000000 b 000068 h occp1 lower output compare register (ch.1) r/w 00000000 b 000069 h higher output compare register (ch.1) 00000000 b 00006a h occp2 lower output compare register (ch.2) r/w 00000000 b 00006b h higher output compare register (ch.2) 00000000 b 00006c h occp3 lower output compare register (ch.3) r/w 00000000 b 00006d h higher output compare register (ch.3) 00000000 b 00006e h reserved 00006f h romm rom mirror function selection register r/w rom mirror function -------1 b
mb90880 series 29 (continued) address register abbreviation register name r/w resource initial value 000070 h occp4 lower output compare register (ch.4) r/w 16-bit i/o timer output compare (ch.0 to ch.5) 00000000 b 000071 h higher output compare register (ch.4) 00000000 b 000072 h occp5 lower output compare register (ch.5) r/w 00000000 b 000073 h higher output compare register (ch.5) 00000000 b 000074 h ocs01 lower output compare control register (ch.0, ch.1) r/w 0000--00 b 000075 h higher output compare control register (ch.0, ch.1) r/w ---00000 b 000076 h ocs23 lower output compare control register (ch.2, ch.3) r/w 0000--00 b 000077 h higher output compare control register (ch.2, ch.3) r/w ---00000 b 000078 h ocs45 lower output compare control register (ch.4, ch.5) r/w 0000--00 b 000079 h higher output compare control register (ch.4, ch.5) r/w ---00000 b 00007a h ipcp0 lower input capture data register (ch.0) r 6-bit i/o timer input capture (ch.0, ch.1) xxxxxxxx b 00007b h higher input capture data register (ch.0) r xxxxxxxx b 00007c h ipcp1 lower input capture data register (ch.1) r xxxxxxxx b 00007d h higher input capture data register (ch.1) r xxxxxxxx b 00007e h ics01 input capture control status register r/w 00000000 b 00007f h ice01 input capture edge register r ------xx b 000080 h tcdt lower timer counter data register r/w 16-bit i/o timer free-run timer 00000000 b 000081 h tcdt higher timer counter data register r/w 00000000 b 000082 h tccs timer control status register r/w 00000000 b 000083 h tccs timer control status register r/w xx-00000 b 000084 h cpclr lower compare clear register r/w xxxxxxxx b 000085 h higher compare clear register xxxxxxxx b 000086 h to 00009a h reserved 00009b h dcsr dmac descriptor channel specification register r/w dmac 00000000 b 00009c h dsrl dmac lower status register r/w dmac 00000000 b 00009d h dsrh dmac higher status register r/w dmac 00000000 b
mb90880 series 30 (continued) address register abbreviation register name r/w resource initial value 00009e h pacsr0 address detection control status register 0 r/w address match detection function 00000000 b 00009f h dirr delayed interrupt source generation/ release register r/w delayed interrupt generation module -------0 b 0000a0 h lpmcr low power consumption mode control register w, r/w low power consumption 00011000 b 0000a1 h ckscr clock selection register r, r/w 11111100 b 0000a2 h , 0000a3 h reserved 0000a4 h dssr dmac stop status register r/w dmac 00000000 b 0000a5 h arsr auto ready function selection register w external pin 0011--00 b 0000a6 h hacr external address output control register w ******** b 0000a7 h epcr bus control signal selection register w 1000*10- b 0000a8 h wdtc watchdog timer control register r, w watchdog timer xxxxx111 b 0000a9 h tbtc time base timer control regist er w, r/w time base timer 1xx00100 b 0000aa h wtc watch timer control regist er r, r/w watch timer 10001000 b 0000ab h reserved 0000ac h derl dmac lower enable register r/w dmac 00000000 b 0000ad h derh dmac higher enable register r/w 00000000 b 0000ae h fmcs flash memory control status regi ster w, r/w flash memory i/f 000x0000 b 0000af h prohibited 0000b0 h icr00 interrupt control register 00 w, r/w interrupt control 00000111 b 0000b1 h icr01 interrupt control register 01 w, r/w 00000111 b 0000b2 h icr02 interrupt control register 02 w, r/w 00000111 b 0000b3 h icr03 interrupt control register 03 w, r/w 00000111 b 0000b4 h icr04 interrupt control register 04 w, r/w 00000111 b 0000b5 h icr05 interrupt control register 05 w, r/w 00000111 b 0000b6 h icr06 interrupt control register 06 w, r/w 00000111 b 0000b7 h icr07 interrupt control register 07 w, r/w 00000111 b 0000b8 h icr08 interrupt control register 08 w, r/w 00000111 b 0000b9 h icr09 interrupt control register 09 w, r/w 00000111 b 0000ba h icr10 interrupt control register 10 w, r/w 00000111 b 0000bb h icr11 interrupt control register 11 w, r/w 00000111 b 0000bc h icr12 interrupt control register 12 w, r/w 00000111 b 0000bd h icr13 interrupt control register 13 w, r/w 00000111 b
mb90880 series 31 (continued) address register abbreviation register name r/w resource initial value 0000be h icr14 interrupt control register 14 w, r/w interrupt control 00000111 b 0000bf h icr15 interrupt control register 15 w, r/w 00000111 b 0000c0 h cmr0 chip select area mask register 0 r/w chip select function 00001111 b 0000c1 h car0 chip select area register 0 r/w interrupt control 11111111 b 0000c2 h cmr1 chip select area mask register 1 r/w 00001111 b 0000c3 h car1 chip select area register 1 r/w 11111111 b 0000c4 h cmr2 chip select area mask register 2 r/w 00001111 b 0000c5 h car2 chip select area register 2 r/w 11111111 b 0000c6 h cmr3 chip select area mask register 3 r/w 00001111 b 0000c7 h car3 chip select area register 3 r/w 11111111 b 0000c8 h cscr chip select control register r/w ----000* b 0000c9 h calr chip select active level register r/w ----0000 b 0000ca h to 0000ce h reserved 0000cf h pllos pll output selection register w pll ------x0 b 0000d0 h bapl dma buffer address pointer (low) r/w dmac xxxxxxxx b 0000d1 h bapm dma buffer address pointer (middle) r/w xxxxxxxx b 0000d2 h baph dma buffer address pointer (high) r/w xxxxxxxx b 0000d3 h macs dma control register r/w xxxxxxxx b 0000d4 h ioal dmai/o register address pointer (low) r/w xxxxxxxx b 0000d5 h ioah dmai/o register address pointer (high) r/w xxxxxxxx b 0000d6 h dctl dma data counter (low) r/w xxxxxxxx b 0000d7 h dcth dma data counter (high) r/w xxxxxxxx b 0000d8 h to 0000df h reserved 0000e0 h enir0 interrupt/dtp enable register 0 r/w dtp / external interrupt 00000000 b 0000e1 h eirr0 interrupt/dtp source register 0 r/w xxxxxxxx b 0000e2 h elvr0 request level setting register 0 r/w 00000000 b 0000e3 h request level setting register 0 r/w 00000000 b 0000e4 h enir1 interrupt/dtp enable register 1 r/w dtp / external interrupt 00000000 b 0000e5 h eirr1 interrupt/dtp source register 1 r/w xxxxxxxx b 0000e6 h elvr1 request level setting register 1 r/w 00000000 b 0000e7 h request level setting register 1 r/w 00000000 b
mb90880 series 32 (continued) address register abbreviation register name r/w resource initial value 0000e8 h enir2 interrupt/dtp enable register 2 r/w dtp / external interrupt xxxx0000 b 0000e9 h eirr2 interrupt/dtp source register 2 r/w xxxxxxxx b 0000ea h elvr2 request level setting register 2 r/w 00000000 b 0000eb h request level setting register 2 r/w 00000000 b 0000ec h to 0000ef h reserved 0000f0 h to 0000ff h external area 000100 h to # h * ram area 007900 h pcntl0 ppg0 lower control status register r/w 16-bit ppg0 00000000 b 007901 h pcnth0 ppg0 higher control status register r/w 00000001 b 007902 h pcntl1 ppg1 lower control status register r/w 16-bit ppg1 00000000 b 007903 h pcnth1 ppg1 higher control status register r/w 00000001 b 007904 h pcntl2 ppg2 lower control status register r/w 16-bit ppg2 00000000 b 007905 h pcnth2 ppg2 higher control status register r/w 00000001 b 007906 h pcntl3 ppg3 lower control status register r/w 16-bit ppg3 00000000 b 007907 h pcnth3 ppg3 higher control status register r/w 00000001 b 007908 h pcntl4 ppg4 lower control status register r/w 16-bit ppg4 00000000 b 007909 h pcnth4 ppg4 higher control status register r/w 00000001 b 00790a h pcntl5 ppg5 lower control status register r/w 16-bit ppg5 00000000 b 00790b h pcnth5 ppg5 higher control status register r/w 00000001 b 00790c h pcntl6 ppg6 lower control status register r/w 16-bit ppg6 00000000 b 00790d h pcnth6 ppg6 higher control status register r/w 00000001 b 00790e h pcntl7 ppg7 lower control status register r/w 16-bit ppg7 00000000 b 00790f h pcnth7 ppg7 higher control status register r/w 00000001 b 007910 h ppgdiv ppg0 output division setting register r/w 16-bit ppg0 11111100 b 007911 h reserved 007912 h pdcrl0 ppg0 down counter register r 16-bit ppg0 11111111 b 007913 h pdcrh0 11111111 b 007914 h pcsrl0 ppg0 period setting register w 11111111 b 007915 h pcsrh0 11111111 b
mb90880 series 33 (continued) address register abbreviation register name r/w resource initial value 007916 h pudutl0 ppg0 duty setting register w 16-bit ppg0 00000000 b 007917 h puduth0 00000000 b 007918 h disabled 007919 h disabled 00791a h pdcrl1 ppg1 down counter register r 16-bit ppg1 11111111 b 00791b h pdcrh1 11111111 b 00791c h pcsrl1 ppg1 period setting register w 11111111 b 00791d h pcsrh1 11111111 b 00791e h pudutl1 ppg1 duty setting register w 00000000 b 00791f h puduth1 00000000 b 007920 h disabled 007921 h disabled 007922 h pdcrl2 ppg2 down counter register r 16-bit ppg2 11111111 b 007923 h pdcrh2 11111111 b 007924 h pcsrl2 ppg2 period setting register w 11111111 b 007925 h pcsrh2 11111111 b 007926 h pudutl2 ppg2 duty setting register w 00000000 b 007927 h puduth2 00000000 b 007928 h disabled 007929 h disabled 00792a h pdcrl3 ppg3 down counter register r 16-bit ppg3 11111111 b 00792b h pdcrh3 11111111 b 00792c h pcsrl3 ppg3 period setting register w 11111111 b 00792d h pcsrh3 11111111 b 00792e h pudutl3 ppg3 duty setting register w 00000000 b 00792f h puduth3 00000000 b 007930 h disabled 007931 h disabled 007932 h pdcrl4 ppg4 down counter register r 16-bit ppg4 11111111 b 007933 h pdcrh4 11111111 b 007934 h pcsrl4 ppg4 period setting register w 11111111 b 007935 h pcsrh4 11111111 b 007936 h pudutl4 ppg4 duty setting register w 00000000 b 007937 h puduth4 00000000 b
mb90880 series 34 (continued) address register abbreviation register name r/w resource initial value 007938 h disabled 007939 h disabled 00793a h pdcrl5 ppg5 down counter register r 16-bit ppg5 11111111 b 00793b h pdcrh5 11111111 b 00793c h pcsrl5 ppg5 period setting register w 11111111 b 00793d h pcsrh5 11111111 b 00793e h pudutl5 ppg5 duty setting register w 00000000 b 00793f h puduth5 00000000 b 007940 h disabled 007941 h disabled 007942 h pdcrl6 ppg6 down counter register r 16-bit ppg6 11111111 b 007943 h pdcrh6 11111111 b 007944 h pcsrl6 ppg6 period setting register w 11111111 b 007945 h pcsrh6 11111111 b 007946 h pudutl6 ppg6 duty setting register w 00000000 b 007947 h puduth6 00000000 b 007948 h disabled 007949 h disabled 00794a h pdcrl7 ppg7 down counter register r 16-bit ppg7 11111111 b 00794b h pdcrh7 11111111 b 00794c h pcsrl7 ppg7 period setting register w 11111111 b 00794d h pcsrh7 11111111 b 00794e h pudutl7 ppg7 duty setting register w 00000000 b 00794f h puduth7 00000000 b 007950 h disabled 007951 h disabled 007952 h tmcr0 timer control register ch.0 r/w base timer ch.0 00000000 b 007953 h 00000000 b 007954 h stc0 status control register ch.0 r/w 00000000 b 007955 h disabled 007956 h tmr0 timer register ch.0 r/w base timer ch.0 00000000 b / xxxxxxxx b 007957 h 00000000 b / xxxxxxxx b
mb90880 series 35 (continued) address register abbreviation register name r/w resource initial value 007958 h pcsr0/ prll0 period/l-width setting register ch.0 r/w base timer ch.0 xxxxxxxx b 007959 h xxxxxxxx b 00795a h pdut0/ prlh0/ dtbf0 duty/h-width/data buffer register ch.0 r/w xxxxxxxx b / 00000000 b 00795b h xxxxxxxx b / 00000000 b 00795c h tmcr1 timer control register ch.1 r/w base timer ch.1 00000000 b 00795d h 00000000 b 00795e h stc1 status control register ch.1 r/w 00000000 b 00795f h disabled 007960 h tmr1 timer register ch.1 r/w base timer ch.1 00000000 b / xxxxxxxx b 007961 h 00000000 b / xxxxxxxx b 007962 h pcsr1/ prll1 period/l-width setting register ch.1 r/w xxxxxxxx b 007963 h xxxxxxxx b 007964 h pdut1/ prlh1/ dtbf1 duty/h-width/data buffer register ch.1 r/w xxxxxxxx b / 00000000 b 007965 h xxxxxxxx b / 00000000 b 007966 h tmcr2 timer control register ch.2 r/w base timer ch.2 00000000 b 007967 h 00000000 b 007968 h stc2 status control register ch.2 r/w 00000000 b 007969 h disabled 00796a h tmr2 timer register ch.2 r/w base timer ch.2 00000000 b / xxxxxxxx b 00796b h 00000000 b / xxxxxxxx b 00796c h pcsr2/ prll2 period/l-width setting register ch.2 r/w xxxxxxxx b 00796d h xxxxxxxx b 00796e h pdut2/ prlh2/ dtbf2 duty/h-width/data buffer register ch.2 r/w xxxxxxxx b / 00000000 b 00796f h xxxxxxxx b / 00000000 b 007970 h tmcr3 timer control register ch.3 r/w base timer ch.3 00000000 b 007971 h 00000000 b 007972 h stc3 status control register ch.3 r/w 00000000 b
mb90880 series 36 (continued) address register abbreviation register name r/w resource initial value 007973 h disabled 007974 h tmr3 timer register ch.3 r/w base timer ch.3 00000000 b / xxxxxxxx b 007975 h 00000000 b / xxxxxxxx b 007976 h pcsr3/ prll3 period/l-width setting register ch.3 r/w xxxxxxxx b 007977 h xxxxxxxx b 007978 h pdut3/ prlh3/ dtbf3 duty/h-width/data buffer register ch.3 r/w xxxxxxxx b / 00000000 b 007979 h xxxxxxxx b / 00000000 b 00797a h udcr0 up-down count register (ch.0) r 8/16-bit up-down counter/timer 00000000 b 00797b h udcr1 up-down count register (ch.1) r 00000000 b 00797c h rcr0 reload/compare register (ch.0) w 00000000 b 00797d h rcr1 reload/compare register (ch.1) w 00000000 b 00797e h ccrl0 lower counter control register (ch.0) w, r/w xx00x000 b 00797f h ccrh0 higher counter control register (ch.0) r/w 00000000 b 007980 h ccrl1 lower counter control register (ch.1) w, r/w xx00x000 b 007981 h ccrh1 higher counter control register (ch.1) r/w -0000000 b 007982 h csr0 counter status register (ch.0) r, r/w 00000000 b 007983 h reserved 007984 h csr1 counter status register (ch.1) r, r/w 8/16-bit up-down counter/timer 00000000 b 007985 h to 00798f h reserved 007990 h smr6 serial bus mode register ch.6 r/w multi-function serial ch.6 $$$$$$$$ b 007991 h scr6/ibcr6 serial bus control register / i 2 c bus control register ch.6 r/w $$$$$$$$ b 007992 h escr6/ ibsr6 extended communication control register / i 2 c bus status register ch.6 r/w $$$$$$$$ b 007993 h ssr6 serial status register ch.6 r/w $$$$$$$$ b 007994 h rdr06/ tdr06 transmission/reception data register 0 ch.6 r,w $$$$$$$$ b 007995 h rdr16/ tdr16 transmission/reception data register 1 ch.6 r,w $$$$$$$$ b 007996 h bgr06 baud rate generator register 0 ch.6 r/w $$$$$$$$ b 007997 h bgr16 baud rate generator register 1 ch.6 r/w $$$$$$$$ b
mb90880 series 37 (continued) address register abbreviation register name r/w resource initial value 007998 h isba6 7-bit slave address register ch.6 r/w multi-function serial ch.6 00000000 b 007999 h ismk6 7-bit slave address mask register ch.6 r/w 01111111 b 00799a h pafsr ppg pin assignment switching register r/w ppg pin switching control ----0000 b 00799b h pmssr ppg multi-channel start register r/w ppg multi-start control 00000000 b 00799c h reserved 00799d h p9fsr serial pin switching register 1 r/w multi-function serial pin control -----000 b 00799c h to 0079a1 h reserved 0079a2 h p7fsr serial pin switching register 0 r/w multi-function serial pin control ----000x b 0079a3 h lsyns lin synch field switching register r/w input capture input control 10001000 b 0079a4 h , 0079a5 h reserved 0079a6 h fwr0 flash memory write control register 0 r/w flash memory i/f 00000000 b 0079a7 h fwr1 flash memory write control register 1 r/w 00000000 b 0079a8 h to 0079df h reserved 0079e0 h padr0 detection address register 0 (low) r/w address match detection function xxxxxxxx b 0079e1 h detection address register 0 (middle) xxxxxxxx b 0079e2 h detection address register 0 (high) xxxxxxxx b 0079e3 h padr1 detection address register 1 (low) r/w address match detection function xxxxxxxx b 0079e4 h detection address register 1 (middle) xxxxxxxx b 0079e5 h detection address register 1 (high) xxxxxxxx b 0079e6 h padr2 detection address register 2 (low) r/w address match detection function xxxxxxxx b 0079e7 h detection address register 2 (middle) xxxxxxxx b 0079e8 h detection address register 2 (high) xxxxxxxx b 0079e9 h to 0079ef h reserved 0079f0 h padr3 detection address register 3 (low) r/w address match detection function xxxxxxxx b 0079f1 h detection address register 3 (middle) xxxxxxxx b 0079f2 h detection address register 3 (high) xxxxxxxx b
mb90880 series 38 (continued) explanation on r/w r/w : readable/writable r : read only w : write only explanation on initial value 0 : the initial value of this bit is ?0?. 1 : the initial value of this bit is ?1?. x : the initial value of this bit is undefined. - : this bit is not used. * : the initial value of this bit is ?1? or ?0?. it varies depending on the mode pin (md2, md1 or md0 pin) . + : the initial value of this bit is ?1? or ?0?. $ : the initial value of this bit varies depending on the operation mode of the resource. #h* : varies depending on the ram area of the device. address register abbreviation register name r/w resource initial value 0079f3 h padr4 detection address register 4 (low) r/w address match detection function xxxxxxxx b 0079f4 h detection address register 4 (middle) xxxxxxxx b 0079f5 h detection address register 4 (high) xxxxxxxx b 0079f6 h padr5 detection address register 5 (low) r/w address match detection function xxxxxxxx b 0079f7 h detection address register 5 (middle) xxxxxxxx b 0079f8 h detection address register 5 (high) xxxxxxxx b 0079f9 h to 007fff h reserved
mb90880 series 39 interrupt sources, interrupt vectors and interrupt control registers (continued) interrupt source clearing of ei 2 os dmac channel no. interrupt vector interrupt control register no. address no. address reset ? #08 ffffdc h ?? int9 instruction ? #09 ffffd8 h ?? exception ? #10 ffffd4 h ?? int0 (irq0/1) 0 #11 ffffd0 h icr00 0000b0 h int0 (irq2 to irq7) #12 ffffcc h int0 (irq8 to irq15) #13 ffffc8 h icr01 0000b1 h int0 (irq16 to irq23) #14 ffffc4 h base timer ch.0 (source 0,1) 1 #15 ffffc0 h icr02 0000b2 h base timer ch.1 (source 0,1) 2 #16 ffffbc h base timer ch.2 (source 0,1) 3 #17 ffffb8 h icr03 0000b3 h base timer ch.3 (source 0,1) 4 #18 ffffb4 h ppg0/ppg4 counter borrow 5 #19 ffffb0 h icr04 0000b4 h ppg1/ppg5 counter borrow 6 #20 ffffac h ppg2/ppg6 counter borrow 7 #21 ffffa8 h icr05 0000b5 h ppg3/ppg7 counter borrow 8 #22 ffffa4 h 8/16-bit up-down counter/timer (ch.0/1) compare / underflow / overflow / up-down inversion #23 ffffa0 h icr06 0000b6 h input capture retrieval (ch.0/1) #24 ffff9c h output compare (ch.0/1/2) match #25 ffff98 h icr07 0000b7 h output compare (ch.3/4/5) match #26 ffff94 h a/d converter #27 ffff90 h icr08 0000b8 h overflow in 16-bit free-run timer / compare clear / multi-function serial ch.4/5/6 status 9 #28 ffff8c h multi-function serial ch.4 reception 10 #29 ffff88 h icr09 0000b9 h multi-function serial ch.4 transition 11 #30 ffff84 h multi-function serial ch.5 reception 12 #31 ffff80 h icr10 0000ba h multi-function serial ch.5 transition 13 #32 ffff7c h multi-function serial ch.6 reception 14 #33 ffff78 h icr11 0000bb h multi-function serial ch.6 transition 15 #34 ffff74 h multi-function serial ch.0/1 reception / status #35 ffff70 h icr12 0000bc h multi-function serial ch.0/1 transmission #36 ffff6c h multi-function serial ch.2 reception / status #37 ffff68 h icr13 0000bd h multi-function serial ch.2 transmission #38 ffff64 h
mb90880 series 40 (continued) : the interrupt request flag is not cl eared by the interrupt clear signal. : the interrupt request flag is clea red by the interrupt clear signal. : the interrupt request flag is cleared by the interrup t clear signal. stop request function provided at receiving only. * : flash writing/deletion, the time base time r and watch timer cannot be used simultaneously. note : if a resource has two interrupt sources for the same interrupt number, bo th of the interrupt request flags are cleared by the ei 2 os/ dmac interrupt clear signal. therefore, when either of the two sources for the ei 2 os/ dmac function is used, the other interrupt function ca n not be used. in this case, set the interrupt request enable bit to ?0? in the appropriate res ource and take measures by software polling. interrupt source clearing of ei 2 os dmac channel no. interrupt vector interrupt control register no. address no. address multi-function serial ch.3 reception / status #39 ffff60 h icr14 0000be h multi-function serial ch.3 transmission #40 ffff5c h flash writing/deletion, time base timer, watch timer* #41 ffff58 h icr15 0000bf h delayed interrupt generation module #42 ffff54 h
mb90880 series 41 electrical characteristics 1. absolute maximum ratings *1 : the parameter is based on v ss = av ss = dv ss = 0.0 v. *2 : set av cc , dv cc and avrh to the same voltage. av cc and dv cc must not exceed v cc . also, avrh must not exceed av cc . *3 : v i and v o must not exceed 0.3v. when the maximum current to/fr om an input is limited by using an external component, the i clamp rating supersedes the v i rating. *4 : the maximum output current is defined as the peak va lue of the current of any one of the corresponding pins. (continued) parameter symbol rating unit remarks min max power supply voltage *1 v cc v ss ? 0.3 v ss + 4.0 v dv cc v ss ? 0.3 v ss + 4.0 v dvcc = vcc* 2 av cc v ss ? 0.3 v ss + 4.0 v *2 avrh v ss ? 0.3 v ss + 4.0 v *2 input voltage *1 v i v ss ? 0.3 v ss + 4.0 v *3 v ss ? 0.3 v ss + 7.0 v *3, *8 output voltage *1 v o v ss ? 0.3 v ss + 4.0 v *3 v ss ? 0.3 v ss + 7.0 v *3, *8 maximum clamp current i clamp ? 2.0 + 2.0 ma *7 total maximum clamp current ? i clamp ?? 20 ma *7 ?l? level maximum output cur- rent i ol1 ? 10 ma *4 i ol2 ? 20 ma pa0 to pa3* 4 ?l? level average output current i olav1 ? 3ma*5 i olav2 ? 10 ma pa0 to pa3* 5 ?l? level maximum total output current i ol1 ? 60 ma i ol2 ? 80 ma pa0 to pa3 ?l? level average total output current i olav1 ? 30 ma *6 i olav2 ? 40 ma pa0 to pa3* 6 ?h? level maximum output current i oh1 ?? 10 ma *4 i oh2 ?? 20 ma pa0 to pa3* 4 ?h? level average output current i ohav1 ?? 3ma*5 i ohav2 ?? 10 ma pa0 to pa3* 5 ?h? level maximum total output current i oh1 ?? 60 ma i oh2 ?? 80 ma pa0 to pa3 ?h? level average total output current i ohav1 ?? 30 ma *6 i ohav2 ?? 40 ma pa0 to pa3* 6 power consumption p d ? 320 mw operating temperature t a ? 40 + 85 c storage temperature tstg ? 55 + 150 c
mb90880 series 42 (continued) *5 : the average output current is defined as the value of the average current flowing over 100 ms at any one of the corresponding pins. *6 : the average total output current is defined as the value of the average current flowing over 100 ms at all of the corresponding pins. *7 : ? relevant pins : p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p47, p50 to p57, p60 to p67, p70 to p76, p80 to p87, p90 to p97, pa0 to pa3 ? use within recommended operating conditions. ? use with dc voltage (current) . ? the + b signal should always be applied with a limiting resistance placed between the + b signal and the microcontroller. ? set the limiting resistor value, whether instantaneous or stationary, so that the current to be input to the microcontroller pin does not exceed t he rating during the input of the + b signal. ? note that when the microcontroller drive current is low, such as in the power saving modes, the + b input potential may pass through the protective diode and increase the potential at the vcc pin, and this may affect other devices. ? note that if a + b signal is input when the microcontroller curren t is off (not fixed at 0 v) , the power supply is provided from the pins, so that incomplete operation may result. ? note that if the + b input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be su fficient to operate the power-on reset. ? care must be taken not to leave the + b input pin open. ? note that analog system input/output pins (lcd driv e pins, comparator input pins, etc.) cannot accept + b signal input. ? sample recommended circuit : *8 : p74 to p76 and p80 to p87 can be used as 5v i/f pins. warning: semiconductor devices can be permanently dama ged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximu m ratings. do not exceed any of these ratings. p-ch n-ch v cc r ? input/output equivalent circuit protective diode limiting resistance + b input (0v to 16v)
mb90880 series 43 2. recommended operating conditions (v ss = av ss = 0.0 v) parameter symbol value unit remarks min max power supply voltage v cc dvcc 2.7 3.6 v in normal operation 1.8 3.6 v hold stop status ?h? level input voltage v ih 0.7 v cc v cc + 0.3 v all pins other than v ih2 , v ihs , v ihm and v ihx v ih2 0.7 v cc v ss + 5.8 v p74 to p76, p80 to p87 v ihs 0.8 v cc v cc + 0.3 v hysteresis input pins v ihs2 0.7 v cc v cc + 0.3 v hysteresis input pins (multi-function serial pins) v ihs3 0.7 v cc v cc + 0.3 v cmos input pins (external bus mode input pins) v ihm v cc ? 0.3 v cc + 0.3 v md pin input v ihx 0.8 v cc v cc + 0.3 v x0a and x1a pins ?l? level input voltage v il v ss ? 0.3 0.3 v cc v all pins other than v ils , v ilm and v ihx v ils v ss ? 0.3 0.2 v cc v hysteresis input pins v ils2 v ss ? 0.3 0.3 v cc v hysteresis input pins (multi-function serial pins) v ils3 v ss ? 0.3 0.3 v cc v cmos input pins (external bus mode pins) v ilm v ss ? 0.3 v ss + 0.3 v md pin input v ilx v ss ? 0.3 0.1 v x0a and x1a pins smoothing capacitor c s 0.1 1.0 f use a ceramic capacitor or comparable capacitor of the ac characteristics. bypass capacitor at the vcc pin should be greater than this capacitor. operating temperature t a ? 40 + 85 c c c s ? c pin connection diagram
mb90880 series 44 warning: the recommended operating condi tions are required in order to ensure the normal operation of the semiconductor device. all of the device's electric al characteristics are warranted when the device is operated within these ranges. always use semicon ductor devices within their recommended operating condition ranges. operation outside these ranges ma y adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operat ing conditions, or combinations not represented on the data sheet. users considering a pplication outside the listed conditio ns are advised to contact their fujitsu representatives beforehand.
mb90880 series 45 3. dc characteristics (v cc = 2.7v to 3.6 v, v ss = 0.0 v, t a = ? 40 c to + 85 c) (continued) parameter symbol pin name conditions value unit remarks min typ max ?h? level output voltage v oh all pins except p74 to p76, p80 to p87 and pa 0 t o pa 3 v cc = 3.0 v, i oh = ? 4.0 ma v cc ? 0.5 ?? v p74 to p76, p80 to p87 v cc = 3.0 v, i oh = ? 2.0 ma v cc ? 0.5 ?? v pa 0 t o pa 3 dv cc = 3.0 v, i oh = ? 10.0 ma dv cc ? 0.6 ?? v ?l? level output voltage v ol all pins except p74 to p76, p80 to p87 and pa 0 t o pa 3 v cc = 3.0 v, i ol = 4.0 ma ?? 0.4 v p74 to p76, p80 to p87 v cc = 3.0 v, i oh = ? 2.0 ma ?? 0.4 v pa 0 t o pa 3 dv cc = 3.0 v, i ol = 10.0 ma ?? 0.5 v input leak current i il all input pins v cc = 3.3 v, v ss < v i < v cc ? 10 ?+ 10 a pull-up resistance r pull ?? 25 50 100 k ? evaluation version 15 33 66 k ? flash memory version / mask rom version open-drain output current i leak p31, p32, p34, p35, p43, p44, p46, p47, p72 to p76, p80 to p87, p96, p97 ?? 0.1 10 a
mb90880 series 46 (continued) (v cc = 2.7v to 3.6 v, v ss = 0.0 v, t a = ? 40 c to + 85 c) note : p74 to p76 and p80 to p87 are n-ch open-drain pi ns with controls and normally used at the cmos level. parameter sym- bol pin name conditions value unit min typ max supply current i cc ? v cc = 3.3v; normal internal 25 mhz operation ? 20 28 ma v cc = 3.3v; normal internal 33 mhz operation ? 28 38 ma v cc = 3.3v; internal 25 mhz operation; flash write ? 30 40 ma v cc = 3.3v; internal 33 mhz operation; flash write ? 40 52 ma i ccs ? v cc = 3.3v; internal 25 mhz operation; sleep mode ? 612ma v cc = 3.3v; internal 33 mhz operation; sleep mode ? 10 20 ma i cts ? v cc = 3.3 v; internal 2 mhz, operation; time-base timer ? 0.25 0.9 ma i ccl ? v cc = 3.3v; external 32 khz & internal 8 khz operation; sub-operation (t a = + 25 c) ? 80 200 a i ccls ? v cc = 3.3 v; external 32 mhz, internal 8 mhz operation; sub sleep mode (t a = + 25 c) ? 50 160 a i cct ? v cc = 3.3v; external 32 khz & internal 8 khz operation; watch operation (t a = + 25 c) ? 20 110 a i cch ? t a = + 25 c; stop mode; v cc = 3.3v ? 15 100 a input capacitance c in all pins except avcc, avss, vcc, dvcc, vss, dvss av cc , av ss , v cc , dv cc , v ss , dv ss ? 515pf
mb90880 series 47 4. ac characteristics (1) clock timing ratings (v ss = 0.0 v, t a = ? 40 c to + 85 c) *1 : observe the operating voltage with care. the maximum operating frequency is 25 mhz in mb90f883(s) and mb90f884(s). *2 : input it at a duty ratio of 50 % 3 % . parameter symbol pin name condi- tions value unit remarks min typ max clock frequency f ch x0, x1 ? 3 ? 25 mhz external crystal oscillation ? 3 ? 50 external clock input ? 4 ? 25 pll1 multiplication ? 3 ? 12.5 pll2 multiplication ? 3 ? 6.66 pll3 multiplication ? 3 ? 6.25 pll4 multiplication ? 3 ? 5.5 pll6 multiplication ? 3 ? 4.125 pll8 multiplication f cl x0a, x1a ?? 32.768 ? khz clock cycle time t c x0, x1 ? 15.15 ? 333 ns *1 t cl x0a, x1a ?? 30.5 ? s input clock pulse width p wh p wl x0 ? 5 ?? ns p wlh p wll x0a ?? 15.2 ? s*2 input clock rise/fall time t cr t cf x0 ??? 5ns external clock in use internal operating clock frequency f cp ?? 1.5 ? 33 mhz *1 f cpl ??? 8.192 ? khz internal operating clock cycle time t cp ?? 30.3 ? 666 ns *1 t cpl ??? 122.1 ? s x0, x1 clock timing x0 t c t cf t cr 0.8 v cc 0.2 v cc p wh p wl
mb90880 series 48 x0a, x1a clock timing x0a t cl t cf t cr 0. 8 v cc 0.1 v cc p wlh p wll
mb90880 series 49 3 .6 2.7 3 .0 4 1.5 16 33 16 12 25 8 4 3 4 8 12.5 16 25 20 3 2 50 20 6 1.5 9 1 8 24 5 6 10 40 33 supply voltage v cc (v) normal operating range internal clock f cp (mhz) * 4 internal operating clock fr equency vs. supply voltage pll warranted operating range source oscillator frequency vs. in ternal operating clock frequency source oscillator clock f ch (mhz) internal clock f cp (mhz) * 4 pll warranted operating range notes: ? use the f cp at 4 mhz or higher only for pll1 multiplication. ? for a/d operating frequencies, refer to ?5. a/d converter electrical characteristics?. *1 : when using the inte rnal clock at ?20 mhz < f cp 25 mhz? in pll1, 2, 3 or 4 mult iplication setting, set both of the div2 and pll2 bits to ?1? in the pllos register. example : when the source oscillator freq uency is 24 mhz in pll1 multiplication : ckscr register : cs1 = ?0?, cs0 = ?0? pllos register : div2 = ?1?, pll2 = ?1? example : when the source oscillator freq uency is 6 mhz in pll3 multiplication : ckscr register : cs1 = ?1?, cs0 = ?0? pllos register : div2 = ?1?, pll2 = ?1? *2 : when using the inte rnal clock at ?20 mhz < f cp 25 mhz? in pll 2 or 4 multip lication setting, the following settings can also be used. pll2 multiplication : ckscr register : cs1 = ?0?, cs0 = ?0? pllos register : div2 = ?0?, pll2 = ?1? pll4 multiplication ckscr register : cs1 = ?0?, cs0 = ?1? pllos register : div2 = ?0?, pll2 = ?1? *3 : when using the pll6 or 8 multip lication setting, set div2 to ?0? and pll2 to ?1? in the pllos register. example : when the source oscillator freq uency is 4 mhz in pll6 multiplication : ckscr register : cs1 = ?1?, cs0 = ?0? pllos register : div2 = ?0?, pll2 = ?1? example : when the source oscillator freq uency is 3 mhz in pll8 multiplication : ckscr register : cs1 = ?1?, cs0 = ?1? pllos register : div2 = ?0?, pll2 = ?1? *4 : the maximum operating frequency of mb90f883(s) and mb90f884(s) is 25 mhz. 8 multi- plication* 3 no multiplication 6 multi- plica- tion* 3 3 multi- plication* 1 4 multi- plica- tion * 1, * 2 2 multi- plication* 1, * 2 1 multiplication* 1
mb90880 series 50 ac characteristics are determined using the fo llowing measurement reference voltage values. 0.8 v cc 0.2 v cc 2.4 v 0.8 v 0.7 v cc 0.3 v cc input signal waveform hysteresis input pins pins other than hysteresis input/md input pins output signal waveform output pins
mb90880 series 51 (2) clock output timing (v ss = 0.0 v, t a = ? 40 c to + 85 c) * : t cp is the cycle time for the internal operation clock. refer to (1) ?clock timing ratings?. parameter symbol pin name conditions value unit remarks min max cycle time t cyc clk ? t cp * ? ns clk clk t chcl clk v cc = 3.0 v to 3.6 v t cp * / 2 ? 15 t cp * / 2 + 15 ns f cp = 25 mhz v cc = 2.7 v to 3.3 v t cp * / 2 ? 20 t cp * / 2 + 20 ns f cp = 16 mhz v cc = 2.7 v to 3.3 v t cp * / 2 ? 64 t cp * / 2 + 64 ns f cp = 5 mhz clk t cyc 2.4 v 2.4 v 0.8 v t chcl
mb90880 series 52 (3) reset input ratings (v cc = 2.7 v to 3.6 v, v ss = 0.0 v, t a = ? 40 c to + 85 c) *1 : t cp is the cycle time for the internal operation clock. refer to (1) ?clock timing ratings?. *2 : oscillator oscillation time is the time to reach 90 % amplitude. for a crystal oscilla tor, this is a few to several tens of ms; for a ceramic oscillator, this is several hundred ms to a few ms, and for an external clock this is 0 ms. parameter symbol pin name condi- tions value unit remarks min max reset input time t rstl rst ? 16 t cp * 1 ? ns in normal operation oscillator oscillation time * 2 + 100 s + 16 t cp * 1 ? ms in sub clock, sub-sleep, watch and stop modes 100 ? s in time base timer mode 100 s + 16 t cp r s t x0 0.2 v cc 0.2 v cc t r s tl in sub clock, sub-sleep, watch and stop modes internal operation clock internal reset oscillator oscillation time oscillation stabilization wait time execution of instruction 90 % of amplitude c l measurement conditions for ac ratings pin c l : load capacitance applied to pin during testing clk, ale : c l = 30 pf ad15 to ad00 (address, data bus) , rd , wr , a23 to a00/d15 to d00 : c l = 30 pf
mb90880 series 53 (4) power-on ratings (power-on reset) (v cc = 2.7 v to 3.6 v, v ss = 0.0 v, t a = ? 40 c to + 85 c) * : during the power rise time, v cc must be less than 0.2v. notes : ? the above ratings are values used for power-on reset. ? a power-on reset should be applied by restarting the power supply inside the device. parameter symbol pin name conditions value unit remarks min max power rise time t r vcc ? 0.05 30 ms * power cutoff time t off vcc 1 ? ms for continuous operation vcc vcc vss t r t off 2.7 v 0.2 v 0.2 v 0.2 v a sudden change in the supply volt age may activate a power-on reset. as shown in the following figure, it is reco mmended to apply a smoo th voltage rise with suppressed fluctuation when changing the supply voltage during operation. a rise slope of 50mv/ms or less is recommended. ram data held main power voltage sub supply voltage
mb90880 series 54 (5) bus read timing (v cc = 2.7 v to 3.6 v, v ss = 0.0 v, t a = 0 c to + 70 c) * : t cp is the cycle time for the internal operation clock. refer to (1) ?clock timing ratings?. parameter symbol pin name condi- tions value unit remarks min max ale pulse width t lhll ale ? t cp * / 2 ? 15 ? ns 16 mhz < f cp 25 mhz t cp * / 2 ? 20 ? ns 8 mhz < f cp 16 mhz t cp * / 2 ? 35 ? ns f cp 8 mhz valid address ale time t avll address, ale ? t cp * / 2 ? 17 ? ns t cp * / 2 ? 40 ? ns f cp 8 mhz ale valid address time t llax ale, address ? t cp * / 2 ? 15 ? ns valid address rd time t avrl rd , address ? t cp * ? 25 ? ns valid address valid data input t avdv address / data ? ? 5 t cp * / 2 ? 55 ns ? 5 t cp * / 2 ? 80 ns f cp 8 mhz rd pulse width t rlrh rd ? 3 t cp * / 2 ? 25 ? ns 16 mhz < f cp 25 mhz 3 t cp * / 2 ? 20 ? ns 8 mhz < f cp 16 mhz rd valid data input t rldv rd , data ? ? 3 t cp * / 2 ? 55 ns ? 3 t cp * / 2 ? 80 ns f cp 8 mhz rd data hold time t rhdx rd , data ? 0 ? ns rd ale time t rhlh rd , ale ? t cp * / 2 ? 15 ? ns rd valid address time t rhax address, rd ? t cp * / 2 ? 10 ? ns valid address clk time t avch address, clk ? t cp * / 2 ? 17 ? ns rd clk time t rlch rd , clk ? t cp * / 2 ? 17 ? ns ale rd time t llrl rd , ale ? t cp * / 2 ? 15 ? ns
mb90880 series 55 0. 8 v 0. 8 v 2.4 v 2.4 v 2.4 v 2.4 v 0. 8 v 2.4 v 2.4 v 0. 8 v 2.4 v 0. 8 v 2.4 v 0. 3 v cc 0.7 v cc 0. 3 v cc 0.7 v cc clk ale rd a2 3 to a16 ad15 to ad00 2.4 v t avch t lhll t rhlh t avll t avrl t rldv t rlrh t rhax t rhdx t llax t llrl t rlch t avdv 0. 8 v 2.4 v 0. 8 v 2.4 v 0. 3 v cc 0.7 v cc 0. 3 v cc 0.7 v cc a2 3 to a00 d15 to d00 t rldv t rhax t rhdx t avdv 0. 8 v 2.4 v address read data read data multiplex mode non-multiplex mode
mb90880 series 56 (6) bus write timing (v cc = 2.7 v to 3.6 v, v ss = 0.0 v, t a = 0 c to + 70 c) * : t cp is the cycle time for the internal operation clock. refer to (1) ?clock timing ratings?. parameter symbol pin name condi- tions value unit remarks min max valid address wr time t avwl address, wr ? t cp * ? 15 ? ns wr pulse width t wlwh wrl , wrh ? 3 t cp * / 2 ? 25 ? ns 16 mhz < f cp 25 mhz ? 3 t cp * / 2 ? 20 ? ns 8 mhz < f cp 16 mhz valid data output wr time t dvwh data, wr ? 3 t cp * / 2 ? 15 ? ns wr data hold time t whdx wr , data ? 10 ? ns 16 mhz < f cp 25 mhz ? 20 ? ns 8 mhz < f cp 16 mhz ? 30 ? ns f cp 8 mhz wr valid address time t whax wr , address ? t cp * / 2 ? 10 ? ns wr ale time t whlh wr , ale ? t cp * / 2 ? 15 ? ns wr clk time t wlch wr , clk ? t cp * / 2 ? 17 ? ns
mb90880 series 57 wr (wrl, wrh) 0. 8 v 0. 8 v 2.4 v 2.4 v 2.4 v 2.4 v 0. 8 v 2.4 v 0. 8 v 2.4 v clk ale a2 3 to a16 ad15 to ad00 t whlh t avwl t dvwh t dvwh t wlwh t whax t whdx t wlch 0. 8 v 2.4 v 0. 8 v 2.4 v a2 3 to a00 d15 to d00 t whax t whdx 0. 8 v 2.4 v 0. 8 v 2.4 v 0. 8 v 2.4 v 0. 8 v 2.4 v address write data write data multiplex mode non-multiplex mode
mb90880 series 58 (7) ready input timing (v cc = 2.7 v to 3.6 v, v ss = 0.0 v, t a = 0 c to + 70 c) parameter symbol pin name conditions value unit remarks min max rdy setup time t ryhs rdy ? 35 ? ns ? 70 ? ns f cp = 8 mhz rdy hold time t ryhh ? 0 ? ns t ryhh 2.4 v 2.4 v 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc clk ale rd/wr t ryhs t ryhs when rdy wait is applied (1 cycle) when rdy wait is not applied
mb90880 series 59 (8) hold timing (v cc = 2.7 v to 3.6 v, v ss = 0.0 v, t a = 0 c to + 70 c) * : t cp is the cycle time for the internal operation clock. refer to (1) ?clock timing ratings?. note : it takes one or more cycles fr om when the hrq pin is read to when hak changes. parameter symbol pin name conditions value unit min max pin floating hak time t xhal hak ? 30 t cp * ns hak valid pin time t hahv hak t cp *2 t cp *ns hak t xhal t hahv 2.4 v 0.8 v 2.4 v 2.4 v 0.8 v 0.8 v pins high-z
mb90880 series 60 (9) multi-function serial timing (uart, sio) (v cc = 2.7 v to 3.6 v, v ss = 0.0 v, t a = ? 40 c to + 85 c) *1 : c l is the load capacitance app lied to pins during testing. *2 : t cp is the cycle time for the internal operation clock. refer to (1) ?clock timing ratings?. note : the above ac characteristics are for clk synchronous mode operation. parameter symbol pin name conditions value unit min max serial clock cycle time t scyc ? internal shift clock mode output pin : c l * 1 = 80 pf + 1 ttl 8 t cp * 2 ? ns uck uo delay time t slov ?? 50 + 50 ns valid ui uck t ivsh ? 50 ? ns uck valid ui hold time t shix ? 0 ? ns serial clock ?h? pulse width t shsl ? external shift clock mode output pin : c l * 1 = 80 pf + 1 ttl 4 t cp * 2 ? ns serial clock ?l? pulse width t slsh ? 4 t cp * 2 ? ns uck uo delay time t slov ?? 50 ns valid ui uck t ivsh ? 50 ? ns uck valid ui hold time t shix ? 50 ? ns internal shift clock mode external shift clock mode uck uo ui t scyc t slov t ivsh t shix 0.8 v 0.8 v 2.4 v 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc uck uo ui t s l s h t s h s l t s lov t iv s h t s hix 0.2 v cc 0.2 v cc 0. 8 v cc 0. 8 v cc 2.4 v 0. 8 v 0. 8 v cc 0.2 v cc 0. 8 v cc 0.2 v cc
mb90880 series 61 (10) multi-function serial timing (i 2 c) a. master mode operation ( v cc = 2.7 v to 3.6 v , v ss = 0.0 v , t a = ? 40 c to + 85 c) parameter symbol condi- tions standard mode high-speed mode * 3 unit minmaxminmax scl clock frequency f scl r=1k ? c=50pf* 4 0 100 0 400 khz scl clock ?l? width t low 4.7 ? 4.7 ? s scl clock ?h? width t high 4.0 ? 4.0 ? s bus-free time between ?stop? condition and ?start? condition t bus 4.7 ? 1.3 ? s repeat ?start? condition setup time scl sda t susta 4.7 ? 0.6 ? s (repeat) ?start? condition hold time sda scl t hdsta 4.0 ? 0.6 ? s ?stop? condition setup time scl sda t susto 4.0 ? 0.6 ? s data hold time scl sda t hddat 2tcp* 1 ? 2tcp* 1 ? s data setup time sda scl t sudat 250 ? 100* 2 ? ns
mb90880 series 62 b. slave mode operation ( v cc = 2.7 v to 3.6 v , v ss = 0.0 v , t a = ? 40 c to + 85 c) *1 : t cp is the cycle time for the internal operation clock. refer to (1) ?clock timing ratings?. *2 : the high-speed mode i 2 c bus device can be used in a standard mode i 2 c bus system. however, the device must satisfy the required condition ?t sudat 250 ns?. if the device does not extend the ?l? period of the scl signal, the succeeding data must be output to the sda line before a period of 1250 ns (the maximum time of sda/scl rise + t sudat ) in which the scl line is open. *3 : set the internal operation clock to 6mhz or higher when using this over 100khz. *4 : ?r? and ?c? are the pull-up resistanc e and load capacitance of the scl/sda lines. parameter symbol condi- tions standard mode high-speed mode * 3 unit minmaxminmax scl clock frequency f scl r=1k ? c=50pf* 4 01000400khz scl clock ?l? width t low 4.7 ? 1.3 ? s scl clock ?h? width t high 4.0 ? 0.6 ? s bus-free time between ?stop? condition and ?start? condition t bus 4.7 ? 1.3 ? s repeat ?start? condition setup time scl sda t susta 4.7 ? 0.6 ? s (repeat) ?start? condition hold time sda scl t hdsta 4.0 ? 0.6 ? s ?stop? condition setup time scl sda t susto 4.0 ? 0.6 ? s data hold time scl sda t hddat 2tcp* 1 ? 2tcp* 1 ? s data setup time sda scl t sudat 250 ? 100* 2 ? ns
mb90880 series 63 note: the specification for the input data setup time of the device which is connected to the bus may not be satisfied, depending on the load capacitance and pull-up resistance. if the specification of the input data setup time can no t be satisfied, adjust the pull-up resistance of sda and scl. sda scl 6 tcp note on sda/scl setup time input data setup time sda scl t bus t low f scl t hddat t high t sudat t hdsta t susta t hdsta t susto timing definition
mb90880 series 64 (11) timer input timing (v cc = 2.7 v to 3.6 v, v ss = 0.0 v, t a = ? 40 c to + 85 c) *: t cp is the cycle time for the internal operatio n clock. refer to (1) ?clock timing ratings?. (12) timer output timing (v cc = 2.7 v to 3.6 v, v ss = 0.0 v, t a = ? 40 c to + 85 c) parameter symbol pin name conditions value unit min max input pulse width t tiwh t tiwl in0, in1, tio0 to tio3 ? 4 t cp * ? ns parameter symbol pin name conditions value unit min max clk change time ppg0 to ppg5 change time out0 to out5 change time t to ppg0 to ppg7, out0 to out5, tio0 to tio3 load condition : 80 pf 30 ? ns in0, in1 tio0 to tio 3 0. 8 v cc 0. 8 v cc 0.2 v cc 0.2 v cc t tiwh t tiwl clk 0. 3 v cc ppg0 to ppg7 out0 to out5 tio0 to tio 3 0.7 v cc 0.7 v cc t to
mb90880 series 65 (13) trigger input timing (v cc = 2.7 v to 3.6 v, v ss = 0.0 v, t a = ? 40 c to + 85 c) *: t cp is the cycle time for the internal operatio n clock. refer to (1) ?clock timing ratings?. parameter symbol pin name conditions value unit remarks min max input pulse width t trgh t trgl adtg , irq0 to irq7 ? 5 t cp * ? ns in normal operation 1 ? s in stop mode 0. 8 v cc irq0 to irq7 adtg 0. 8 v cc 0.2 v cc 0.2 v cc t trgh t trgl
mb90880 series 66 (14) chip select output timing (v cc = 2.7 v to 3.6 v, v ss = 0.0 v, t a = ? 40 c to + 85 c) *: t cp is the cycle time for the internal operatio n clock. refer to (1) ?clock timing ratings?. note : the chip select output signal changes simultaneously due to the internal bus configuration; therefore, this may generate a bus wait. ac cannot be warranted betwe en the ale output signal and the chip select output signal. parameter symbol pin name conditions value unit min max chip select output valid time rd t svrl cs0 to cs3, rd ? t cp * / 2 ? 7 ? ns chip select output valid time wr t svwl cs0 to cs3, wrh , wrl ? t cp * / 2 ? 7 ? ns rd chip select output valid time t rhsv rd , cs0 to cs3 ? t cp * / 2 ? 17 ? ns wr chip select output valid time t whsv wrh , wrl , cs0 to cs3 ? t cp * / 2 ? 17 ? ns t s vrl t s vwl t wh s v t rh s v 0. 8 v 0. 8 v 2.4 v 2.4 v 2.4 v 2.4 v 0. 8 v 0. 8 v rd a2 3 to a16 c s 0 to c s3 d15 to d00 wrh, wrl d15 to d00 read data write data un- defined
mb90880 series 67 5. a/d converter electrical characteristics (v cc = av cc = 2.7 v to 3.6 v, v ss = av ss = 0.0 v, 2.7 v avrh, t a = ? 40 c to + 85 c) *1 : time per channel *2 : current when the a/d converter is not in operation and the cpu is stopped (v cc = av cc = avrh = 3.0 v ) parameter symbol pin name value unit remarks min standard max resolution ?? ? ? 10 bit total error ?? ? ? 3.0 lsb linear error ?? ? ? 2.5 lsb differential linear error ?? ? ? 1.9 lsb zero transition voltage v ot an0 to an7 av ss ? 1.5 lsb av ss + 0.5 lsb av ss + 2.5 lsb v full-scale transition voltage v fst an0 to an7 avrh ? 3.5 lsb avrh ? 1.5 lsb avrh + 0.5 lsb v sampling time t smp ? 1.2 ?? s*1 compare time t cmp ? 1.8 ?? s*1 conversion time t cnv ? 3.0 ?? s*1 analog port input current i ain an0 to an7 ? 3.0 ? + 3.0 a analog input voltage v ain an0 to an7 av ss ? avrh v reference voltage ? avrh av ss + 2.2 ? av cc v supply current i a avcc ? 1.9 3.7 ma i ah avcc ?? 5 *2 a reference voltage supply current i r avrh ? 520 720 a i rh avrh ?? 5 *2 a inter-channel variation ? an0 to an7 ?? 4lsb
mb90880 series 68 ? external impedance and sampling time for analog input this is an a/d converter with a sample hold function. if hi gh external impedance is preventing it from securing sufficient sampling time, a sufficient an alog voltage will not be charged in t he internal sample hold capacitor, affecting the accuracy of the a/d conversion. in orde r to satisfy the a/d conversion accuracy specifications, adjust the register values and oper ating frequency or decrease the extern al impedance so that the sampling time becomes longer than the minimum value, based on the relationship between the external impedance and the minimum sampling time. if a sufficient sampling time cannot be secured, connect a capacitor with a ca- pacitance of approximately 0.1 f to the analog input pin. ? errors : as | avrh ? av ss | decreases, the absol ute error increases. r c turned on during sampling on analog input comparator note : these are reference values. model diagram of analog input circuit rc 12.2k ? (max) 8.5pf (max) 0 5 10 15 20 25 3 0 3 5 0 10 20 3 0 40 50 60 70 8 0 90 100 012 3 4567 8 0 2 4 6 8 10 12 14 16 1 8 20 relation between external impedance and minimum sampling time external impedance [k ? ] external impedance [k ? ] [external impedance = 0 k ? to 100 k ? ] minimum sampling time [ s] minimum sampling time [ s] [external impedance = 0 k ? to 20 k ? ] flash memory device mask rom device flash memory device mask rom device
mb90880 series 69 6. definition of a/d converter terms (continued) resolution : analog variation that is recognized by an a/d converter. non linearity error : deviation between a line across ze ro-transition line ( ?00 0000 0000? ?00 0000 0001? ) and full-scale transition line ( ?11 1111 1110? ?11 1111 1111? ) and actual conversion characteristics. differential linearity error : deviation of input voltage, which is required fo r changing output code by 1 lsb, from an ideal value. total error : difference between an actual value and a theoretical valu e. a total error includes zero tran- sition error, full-scale transition error, and linear error. 3ff h 3fe h 3fd h 004 h 003 h 002 h 001 h av ss avrh v nt 1.5 lsb 0.5 lsb {1 lsb (n ? 1) + 0.5 lsb} actual conversion characteristics (actual measurement value) ideal characteristics actual conversion characteristics total error total error of digital output ?n? = v nt ? {1 lsb (n ? 1) + 0.5 lsb} 1 lsb [lsb] 1 lsb (ideal value) = avrh ? av ss 1024 [v] v ot (ideal value) = av ss + 0.5 lsb [v] v fst (ideal value) = avrh ? 1.5 lsb [v] v nt : a voltage at which digital output transits from (n ? 1) h , n h . analog input digital output
mb90880 series 70 (continued) ? flash memory write/erase characteristics * : value converted from the evaluation result of technol ogy reliability (the arrhenius equation is used to convert the high-temperature high-speed test result into the average temperature + 85 c.) parameter conditions value unit remarks min standard max sector erase time t a = + 25 c, v cc = 3.0 v ? 0.9 3.6 s excludes internal write time before erase operation. chip erase time ? 6.2 ? s excludes internal write time before erase operation. byte (16-bit width) write time ? 23 ? s excludes overhead time at system level. number of write/erase cycles ? 10000 ?? cycle flash memory data hold time average t a = + 85 c 100000 ?? h* 3 ff h 3 fe h 3 fd h 004 h 00 3 h 002 h 001 h av ss avrh av ss avrh (n + 1) h n h (n ? 1) h (n ? 2) h { 1 l s b (n ? 1) + v ot } v ot ( a ct ua l me asu rement v a l u e ) act ua l conver s ion ch a r a cteri s tic s act ua l conver s ion ch a r a cteri s tic s ide a l ch a r a cteri s tic s act ua l conver s ion ch a r a cteri s tic s act ua l conver s ion ch a r a cteri s tic s ide a l ch a r a cteri s tic s v f s t ( a ct ua l me asu rement v a l u e) v nt ( a ct ua l me asu rement v a l u e) v nt ( a ct ua l me asu rement v a l u e) v (n + 1) t ( a ct ua l me asu rement v a l u e) linearity error differential linearity error non linearity error of digital output n = v nt ? {1 lsb (n ? 1) + v ot } 1 lsb [lsb] differential linearity error of digital output n = v ( n+1 ) t ? v nt 1 lsb ? 1 lsb [lsb] v fst ? v ot 1022 [v] 1 lsb = v ot : voltage at which digital output transits from ?000 h ? to ?001 h .? v fst : voltage at which digital output transits from ?3fe h ? to ?3ff h .? analog input digital output analog input digital output
mb90880 series 71 ordering information part number package remarks mb90f882pf mb90f883pf mb90f883apf mb90f884pf mb90f884apf mb90882pf mb90883pf MB90884PF mb90f882spf mb90f883spf mb90f883aspf mb90f884spf mb90f884aspf mb90882spf mb90883spf mb90884spf 100-pin plastic qfp (fpt-100p-m06) with s : single clock product (without sub clock) without s : dual clock product (with sub clock) mb90f882pmc mb90f883pmc mb90f883apmc mb90f884pmc mb90f884apmc mb90882pmc mb90883pmc mb90884pmc mb90f882spmc mb90f883spmc mb90f883aspmc mb90f884spmc mb90f884aspmc mb90882spmc mb90883spmc mb90884spmc 100-pin plastic lqfp (fpt-100p-m20) mb90v880-101cr-es mb90v880-102cr-es mb90v880a-101cr-es mb90v880a-102cr-es 299-pin ceramic pga (pga-299c-a01) evaluation product 101 : single clock product (without sub clock) 102 : dual clock product (with sub clock)
mb90880 series 72 package dimensions please confirm the latest package dimension by following url. http://edevice.fujitsu.com/fj/datasheet/ef-ovpklv.html (continued) 100-pin pl as tic lqfp le a d pitch 0.50 mm p a ck a ge width p a ck a ge length 14.0 mm 14.0 mm le a d s h a pe g u llwing s e a ling method pl as tic mold mo u nting height 1.70 mm m a x weight 0.65 g code (reference) p-lfqfp100-14 14-0.50 100-pin pl as tic lqfp (fpt-100p-m20) (fpt-100p-m20) c 2005 fujit s u limited f1000 3 1 s -c-2-1 14.00 0.10(.551 .004) s q 16.00 0.20(.6 3 0 .00 8 ) s q 1 25 26 51 76 50 75 100 0.50(.020) 0.20 0.05 (.00 8 .002) m 0.0 8 (.00 3 ) 0.145 0.055 (.0057 .0022) 0.0 8 (.00 3 ) "a" index .059 ? .004 +.00 8 ? 0.10 +0.20 1.50 (mo u nting height) 0 ? ~ 8 ? (0.50(.020)) (.024 .006) 0.60 0.15 0.25(.010) 0.10 0.10 (.004 .004) det a il s of "a" p a rt ( s t a nd off) * dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s note 1) * : the s e dimen s ion s do not incl u de re s in protr us ion. note 2) pin s width a nd pin s thickne ss incl u de pl a ting thickne ss . note 3 )pin s width do not incl u de tie ba r c u tting rem a inder.
mb90880 series 73 (continued) please confirm the latest package dimension by following url. http://edevice.fujitsu.com/fj/datasheet/ef-ovpklv.html 100-pin pl as tic qfp le a d pitch 0.65 mm p a ck a ge width p a ck a ge length 14.00 20.00 mm le a d s h a pe g u llwing s e a ling method pl as tic mold mo u nting height 3 . 3 5 mm max code (reference) p-qfp100-14 20-0.65 100-pin pl as tic qfp (fpt-100p-m06) ( fpt-100p-m06 ) c 2002 fujit s u limited f10000 8s -c-5-5 1 3 0 3 1 50 51 8 0 8 1 100 20.000.20(.7 8 7.00 8 ) 2 3 .900.40(.941.016) 14.000.20 (.551.00 8 ) 17.900.40 (.705.016) index 0.65(.026) 0. 3 20.05 (.01 3 .002) m 0.1 3 (.005) "a" 0.170.06 (.007.002) 0.10(.004) det a il s of "a" p a rt (.0 3 5.006) 0. 88 0.15 (.0 3 1.00 8 ) 0. 8 00.20 0.25(.010) 3 .00 +0. 3 5 ?0.20 +.014 ?.00 8 .11 8 (mo u nting height) 0.250.20 (.010.00 8 ) ( s t a nd off) 0~ 8 ? * * dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s . note 1) * : the s e dimen s ion s do not incl u de re s in protr us ion. note 2) pin s width a nd pin s thickne ss incl u de pl a ting thickne ss . note 3 ) pin s width do not incl u de tie ba r c u tting rem a inder.
mb90880 series 74 main changes in this edition the vertical lines marked in the left side of the page show the changes. page section change results ?? added the following part numbers: mb90f883a (s), mb90f884a (s) 3 product lineup added the following details to the cpu functions: ?maximum operating frequency is 25 mhz in mb90f883 (s) , mb90f884 (s)? added the following details to the base timer: ?in mb90f883(s) and mb90f884(s), p24/tio0, p25/tio1, p26/tio2, and p27/tio3 canno t be used as input function.? 4 added the "flash memory" item 21 handling devices added "13. note of mb90f883 (s), mb90f884 (s)" 43 electrical characteristics 2. recommended operating conditions added the "smoothing capacitor" item added the " c pin connection diagram" 46 electrical characteristics 3. dc characteristics added the "i cts " and "i ccls " items to the supply current changed supply current ratings: i ccs internal 25 mhz operation; typ 9 6, max 16 12 i ccs internal 33 mhz operation; typ 12 10, max 22 20 i ccl typ 70 80 i cct typ 15 20 i cch ty p 1 0 15 47 electrical characteristics 4. ac characteristics (1) clock timing ratings added the following details to footnote 1 of the table: ?the maximum operating frequency is 25 mhz in mb90f883(s) and mb90f884(s).? 71 ordering information added the following part numbers: mb90f883apf, mb90f884apf, mb90f883aspf, mb90f884aspf, mb90f883apmc, mb90f884apmc, mb90f883aspmc, mb90f884aspmc added the following details to the remarks: with s : single clock product (without sub clock) without s : dual clock product (with sub clock) added the mb90v880 item
mb90880 series f0702 the information for microcontroller suppor ts is shown in the following homepage. http://www.fujitsu.com/global/s ervices/microelectronics/produ ct/micom/support/index.html fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any ot her right of fujitsu or any third party or does fujitsu warrant non-in fringement of any third-party?s intellectual property right or othe r right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremel y high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, ai rcraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon syst em), or (2) for use requiring extremely high reliability (i.e., su bmersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design m easures into your facility and equipment such as redundancy, fi re protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. the company names and brand names herein are the trademarks or registered trademarks of their respective owners. edited business promotion dept.

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